Semiconductor memory apparatus
View Patent ↗A semiconductor memory apparatus includes: a data output signal transmitter configured to receive a data signal and a data mask signal and transmit a data output signal through a global data line, the data output signal being outputted by determining whether the data signal is masked or not; and a write driver configured to receive the data output signal through the global data line and input the received data output signal to a local data line corresponding to the data output signal.
1. A semiconductor memory apparatus comprising:
a data input unit configured to receive a data signal and transmit the received data signal through a global data line;
a data mask input unit configured to receive a data mask signal and transmit the received data mask signal through a global data mask line;
a repeater configured to receive the data signal and the data mask signal through the global data line and the global data mask line, respectively, and transmit a data output signal through the global data line, wherein the data output signal is transmitted if the data signal is not masked; and
a write driver configured to receive the data output signal transmitted from the repeater through the global data line and input the received signal to a local data line.
2. The semiconductor memory apparatus according to claim 1 , wherein the repeater comprises:
a data input strobe signal generation unit configured to be enabled by a write enable signal and generate a data input strobe signal;
a data masking determination unit configured to receive the data input strobe signal, the data signal and the data mask signal, and determine whether the data signal is masked or not; and
an amplification unit configured to amplify the data output signal which is outputted as a determination result from the data masking determination unit.
3. The semiconductor memory apparatus according to claim 2 , wherein the data masking determination unit comprises:
a data mask signal output section configured to output a data mask output signal in response to the data input strobe signal; and
a data signal output section configured to output the data output signal in response to the data mask output signal.
4. The semiconductor memory apparatus according to claim 3 , wherein the data mask signal output section comprises:
a data mask signal output controller configured to receive the data input strobe signal and control an output of the data mask signal;
a latch configured to latch the data mask signal outputted from the mask signal output controller; and
an operation section configured to perform a NOR operation on the data input strobe signal and the data mask signal latched by the latch.
5. The semiconductor memory apparatus according to claim 4 , wherein the data mask signal output controller comprises:
an inverter configured to invert the level of the data input strobe signal; and
a pass gate configured to control whether or not to output the data mask signal in response to the level of the data input strobe signal.
6. The semiconductor memory apparatus according to claim 3 , wherein the data signal output section comprises:
a data signal output controller configured to control an output of the data signal in response to the data mask output signal outputted from the data mask signal output section; and
a latch configured to latch the data signal outputted from the data signal output controller.
7. The semiconductor memory apparatus according to claim 6 , wherein the data signal output controller comprises:
an inverter configured to invert a level of the data mask output signal; and
a pass gate configured to control whether or not to output the data mask signal in response to the level of the data mask output signal.