Method to reduce program disturbs in non-volatile memory cells
View Patent ↗A non-volatile memory and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (V NEG ) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array to reduce a bias applied to a non-volatile memory transistor in an unselected memory cell to reduce program disturb of data programmed in the unselected memory cell due to programming.
1. A method comprising:
coupling a positive voltage to a first global wordline in a first row of a memory array of memory cells and coupling a negative voltage to a first bitline in a first column of the memory array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell; and
coupling a voltage having a magnitude less than the negative voltage to a second global wordline in a second row of the memory array and coupling an inhibit voltage to a second bitline in a second column of the memory array to reduce a bias applied to a non-volatile memory transistor in an un selected memory cell due to the programming of the selected memory cell.
2. The method of claim 1 , wherein the magnitude of the voltage coupled to the second global wordline is less than the negative voltage by an amount at least corresponding to a threshold voltage of a transistor associated with the un selected memory cell.
3. The method of claim 1 , further comprising:
generating, by a digital-to-analog converter (DAC), the voltage having the magnitude less than the negative voltage.
4. The method of claim 1 , further comprising:
at a first time, coupling the negative voltage to the second global wordline in the second row of the memory array,
wherein the voltage having a magnitude less than the negative voltage is coupled to the second global wordline at a second time.
5. The method of claim 4 , wherein the second time corresponds to when a digital-to-analog converter has generated the voltage having the magnitude less than the negative voltage.
6. The method of claim 1 , wherein the voltage having the magnitude less than the negative voltage is coupled to the second global wordline for a duration of the programming of the selected memory cell.
7. The method of claim 1 , further comprising:
generating, by a charge pump, the voltage having the magnitude less than the negative voltage.
8. A method comprising:
applying a positive voltage to a first global wordline in a row of a memory array of memory cells and a negative voltage to a first bitline in a column of the memory array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell; and
applying a voltage having a magnitude less than the negative voltage to a second global wordline in a second row of the memory array and an inhibit voltage to a second bitline in a second column of the memory array to reduce a bias applied to a non-volatile memory transistor in an un selected memory cell that is associated with the programming of the selected memory cell.
9. The method of claim 8 , wherein the magnitude of the voltage applied to the second global wordline is less than the negative voltage by an amount at least corresponding to a threshold voltage of a transistor associated with the un selected memory cell.
10. The method of claim 8 , further comprising:
generating, by a digital-to-analog converter (DAC), the voltage having the magnitude less than the negative voltage.
11. The method of claim 8 , further comprising:
at a first time, applying the negative voltage to the second global wordline in the second row of the memory array,
wherein the voltage having a magnitude less than the negative voltage is applied to the second global wordline at a second time.
12. The method of claim 11 , wherein the second time corresponds to when a digital-to-analog converter has generated the voltage having the magnitude less than the negative voltage.
13. The method of claim 8 , wherein the voltage having the magnitude less than the negative voltage is applied to the second global wordline for a duration of the programming of the selected memory cell.
14. The method of claim 8 , further comprising:
generating, by a charge pump, the voltage having the magnitude less than the negative voltage.
15. A method comprising:
coupling a first global wordline to a memory array of memory cells, wherein the first global wordline is associated with a first row of the memory array of memory cells;
coupling a first bitline to the memory array of memory cells, wherein the first bitline is associated with a first column of the memory array of memory cells, and wherein the first global wordline is to be coupled with a positive voltage and the first bitline is to be coupled with a negative voltage to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell;
coupling a second global wordline to the memory array of memory cells, wherein the second global wordline is associated with a second row of the memory array of memory cells; and
coupling a second bitline to the memory array of memory cells, wherein the second bitline is associated with a second column of the memory array of memory cells, and wherein the second global wordline is to be coupled with a voltage having a magnitude less than the negative voltage and the second bitline is to be coupled to an inhibit voltage to reduce a bias applied to a non-volatile memory transistor in an un selected memory cell due to the programming of the selected memory cell.
16. The method of claim 15 , wherein the magnitude of the voltage coupled to the second global wordline is less than the negative voltage by an amount at least corresponding to a threshold voltage of a transistor associated with the un selected memory cell.
17. The method of claim 15 , further comprising:
generating, by a digital-to-analog converter (DAC), the voltage having the magnitude less than the negative voltage.
18. The method of claim 15 , further comprising:
at a first time, coupling the negative voltage to the second global wordline associated with the second row of the memory array,
wherein the voltage having a magnitude less than the negative voltage is coupled to the second global wordline at a second time.
19. The method of claim 18 , wherein the second time corresponds to when a digital-to-analog converter has generated the voltage having the magnitude less than the negative voltage.
20. The method of claim 15 , wherein the voltage having the magnitude less than the negative voltage is coupled to the second global wordline for a duration of the programming of the selected memory cell.