DUAL DATA RATE BRIDGE CONTROLLER WITH ONE-STEP MAJORITY LOGIC DECODABLE CODES FOR MULTIPLE BIT ERROR CORRECTIONS WITH LOW LATENCY

1 . A memory module comprising:

a bridge controller having a first interface and a second interface, the first interface responsive to commands and data from a host, the second interface coupled to one or more memory components,

wherein the bridge controller is operable to perform multiple-bit error detection and correction on data stored in the one or more memory components.

2 . The memory module of claim 1 , wherein the bridge controller is responsive to a read command from the host and is operable to read the data from the one or more memory components, detect and correct the multiple bit errors, and communicate the corrected data to the host, the bridge controller remaining invisible to the host.

3 . The memory module of claim 1 , wherein the timing of data being available to the one or more memory components from the host being the equivalent timing of data from the host to the memory components through the bridge controller.

4 . The memory module of claim 1 , wherein the memory components are magnetic random access memory (MRAM) or dynamic random access memory (DRAM).

5 . The memory module of claim 1 , wherein the first interface is compliant with the DDR SDRAM Specification.

6 . The memory module of claim 5 , wherein the first interface is compliant with any versions of the DDR SDRAM Specification.

7 . The memory module of claim 1 , wherein the second interface is compliant with the DDR SDRAM Specification.