Memory sense amplifier and column pre-charger
View Patent ↗A memory includes a number of storage elements connected to a pair of bit-lines, a bit-line pre-charging circuit, a sense amplifier connected to the pair of bit-lines through a column-select switch, a transition detection circuit connected to an output of the sense amplifier, and a local pre-charge control circuit connected to the transition detection circuit and having a local pre-charge control signal output connected to the bit-line pre-charging circuit.
1. A memory comprising:
a plurality of storage elements connected to a pair of bit-lines;
a bit-line pre-charging circuit;
a sense amplifier connected to the pair of bit-lines through a column-select switch;
a transition detection circuit connected to an output of the sense amplifier yielding a transition detected signal; and
a local pre-charge control circuit comprising a first input receiving the transition detected signal, and a second input receiving a global pre-charge signal, the local pre-charge control circuit comprising an output yielding a local pre-charge control signal, wherein the output of the local pre-charge control circuit is connected to the bit-line pre-charging circuit, and wherein the local pre-charge control circuit is operable to assert the output of the local pre-charge control circuit based on both the global pre-charge signal and the transition detected signal being in an asserted state.
2. The memory of claim 1 , wherein the sense amplifier comprises an internal node pre-charging circuit controlled by the local pre-charge control signal.
3. The memory of claim 1 , wherein the sense amplifier comprises an enable input connected to a local sense signal, wherein the local sense signal is generated based at least in part on the transition detected signal.
4. The memory of claim 3 , further comprising a local sense amplifier enable circuit comprising a NOR gate having an output yielding the local sense signal, a first input connected to a global sense signal, and a second input connected to the transition detected signal through an inverter.
5. The memory of claim 1 , wherein the local pre-charge control circuit comprises a NOR gate having an output yielding the local pre-charge control signal, a first input connected to a global pre-charge signal and a second input connected to the transition detected signal through an inverter.
6. The memory of claim 1 , wherein the transition detection circuit comprises a read sense circuit configured to pull the transition detected signal down for a predetermined period of time when the output of the sense amplifier transitions, and a pullup transistor connected to the transition detected signal to pull up the transition detected signal when a global sense signal is asserted.
7. The memory of claim 6 , wherein the read sense circuit comprises a pair of transistors connected between the transition detected signal and a ground, a first of the pair of transistors controlled by the output of the sense amplifier, a second of the pair of transistors controlled by a delayed inverted version of the output of the sense amplifier.
8. The memory of claim 7 , wherein the output of the sense amplifier comprises differential signals, wherein the first of the pair of transistors is controlled by a first of the differential signals in the output of the sense amplifier, wherein the second of the pair of transistors is controlled by a delayed inverted version of the first of the differential signals in the output of the sense amplifier, the read sense circuit further comprising a second pair of transistors connected between the transition detected signal and the ground, wherein a first of the second pair of transistors is controlled by a second of the differential signals in the output of the sense amplifier, wherein a second of the pair of transistors is controlled by a delayed inverted version of the second of the differential signals in the output of the sense amplifier.
9. The memory of claim 1 , wherein the transition detection circuit further comprises an output state latch.
10. The memory of claim 1 , wherein the output of the sense amplifier comprises:
a pair of differential signals;
a first pullup transistor connected between a first of the pair of differential signals and power and controlled by a first internal node of the sense amplifier;
a second pullup transistor connected between a second of the pair of differential signals and power and controlled by a second internal node of the sense amplifier;
a third pullup transistor connected between an output node and power, controlled by an inverted version of the first of the pair of differential signals; and
a pulldown transistor connected between the output node and ground, controlled by the second of the pair of differential signals.
11. The memory of claim 10 , wherein the output of the sense amplifier further comprises a pre-discharging transistor connected between each of the pair of differential signals and ground and controlled by a global sense signal.
12. The memory of claim 10 , wherein the output of the sense amplifier further comprises a first cross-coupled pulldown transistor connected between ground and the first of the pair of differential signals, controlled by the second of the pair of differential signals, and a second cross-coupled pulldown transistor connected between ground and the second of the pair of differential signals, controlled by the first of the pair of differential signals.
13. The memory of claim 10 , wherein the output of the sense amplifier further comprises a controlled latch connected to the output node.
14. A method for pre-charging and reading a memory, comprising:
stopping pre-charging in the memory;
amplifying bit-line voltages in a sense amplifier to yield a sense amplifier output;
detecting when the sense amplifier output is ready after the amplifying;
starting the pre-charging based on the sense amplifier output being ready for use; and
disabling the sense amplifier based on the sense amplifier output being ready for use.
15. The method of claim 14 , wherein pre-charging start times across multiple columns in the memory are staggered based on said detecting when the sense amplifier output is ready.
16. The method of claim 14 , wherein detecting when the sense amplifier output is ready comprises detecting a transition on one of a pair of differential output lines that have been pre-discharged.
17. The method of claim 14 , wherein the pre-charging is stopped in response to deassertion of a global pre-charge signal.
18. The method of claim 14 , further comprising enabling the sense amplifier in response to assertion of a global sense signal.
19. The method of claim 14 , further comprising charging a sense amplifier output transition detected signal when a global sense signal is asserted and pulling the sense amplifier output transition detected signal low for a predetermined period after a low to high transition is detected on the sense amplifier output, wherein the pre-charging is started when the sense amplifier output transition detected signal transitions low.
20. A memory comprising:
a plurality of storage elements connected to a pair of bit-lines;
a bit-line pre-charge circuit connected to the pair of bit-lines controlled by a local pre-charge signal;
a sense amplifier comprising a pair of internal nodes connected to the pair of bit-lines through a column-select switch, a pre-charge input connected to the local pre-charge signal, and an enable input connected to a local sense signal;
a pair of output lines connected to power through a pair of pullup transistors each controlled by one of the pair of internal nodes of the sense amplifier;
a transition detection circuit connected to the pair of output lines and configured to assert a transition detected signal for a predetermined period of time in response to a transition from low to high on one of the pair of output lines;
a local enable circuit configured to assert the local sense signal in response to assertion of a global sense signal and to deassert the local sense signal in response to assertion of the transition detected signal; and
a local pre-charge circuit configured to deassert the local pre-charge signal in response to deassertion of a global pre-charge signal and to assert the local pre-charge signal in response to assertion of the transition detected signal.