Electronic device package with vertically integrated capacitors
View Patent ↗A system-in-a-package (SIP) has a semiconductor chip embedded in a dielectric substrate. An inductor is on a top surface of a substrate and is connected to the semiconductor chip. A thin film capacitor may be placed between the inductor and the dielectric substrate. A second thin film capacitor may be placed on the top surface of the semiconductor chip, or be embedded in the dielectric substrate with a thermal pad on a bottom surface of the substrate which is connected to the second thin film capacitor to facilitate heat dissipation.
1. A system in package (SIP) comprising:
a substrate including a semiconductor chip and a first capacitor electrically connected to the semiconductor chip; the semiconductor chip and the first capacitor embedded within the substrate;
an inductor electrically connected to the substrate, the semiconductor chip between the first capacitor and the inductor;
a second capacitor embedded in the substrate, the second capacitor between the semiconductor chip and the inductor in a vertical direction, the vertical direction along a plane of a height of the semiconductor chip, the second capacitor electrically connected and mechanically attached to the semiconductor chip; and
a plastic material covering portions of the substrate and the inductor.
2. The SIP of claim 1 , wherein the first capacitor is attached to a horizontal surface of the semiconductor chip, the horizontal direction being along a length of the semiconductor chip.
3. The SIP of claim 1 , wherein the first capacitor and the second capacitor have a thickness of less than 0.02 millimeters.
4. The SIP of claim 1 , wherein the substrate includes multiple layers with conductive wiring patterns.
5. The SIP of claim 1 , wherein the substrate includes a plurality of leads on one surface.
6. The SIP of claim 1 , wherein the substrate includes a plurality of filled vias connected to the first capacitor.
7. The SIP of claim 5 , wherein the substrate includes a thermal pad attached to the one surface.
8. The SIP of claim 7 , wherein the thermal pad is thermally connected to the at least one capacitor.
9. The SIP of claim 1 , wherein the first capacitor is attached to the semiconductor chip.
10. The SIP of claim 1 , wherein the SIP is a quad flat no lead (QFN) package.
11. The SIP of claim 1 , wherein the semiconductor chip is between the first capacitor and the inductor in a vertical direction, the vertical direction along a height of the semiconductor chip.
12. A system in package (SIP) comprising:
a substrate including a semiconductor chip and a first capacitor embedded within the substrate, the first capacitor mechanically attached to the semiconductor chip;
an inductor electrically connected to the substrate, the inductor including a body portion and two end portions, the two end portions electrically connected to the substrate, the body portion offset from the two end portions defining a gap; and
a second capacitor in the gap and in between the body portion and the semiconductor chip in the substrate, the second capacitor in between the body portion and the semiconductor chip in a vertical direction, the vertical direction along a plane of a height of the semiconductor chip.
13. The SIP of claim 12 further comprising a plastic material covering portions of the substrate, the second capacitor, and the inductor.
14. The SIP of claim 12 , wherein the substrate includes a plurality of leads at one surface.
15. The SIP of claim 12 , wherein the substrate includes a plurality of filled vias connected to the first capacitor.
16. The SIP of claim 12 , wherein the second capacitor has a thickness of less than 0.02 millimeters.
17. A system in package (SIP) comprising:
a substrate including a semiconductor chip and two capacitors attached to two opposite sides of the semiconductor chip, the semiconductor chip and the two capacitors embedded within the substrate, wherein the two capacitors are attached to two horizontal surfaces of the semiconductor chip, the two horizontal surfaces defined along a length of the semiconductor chip;
an inductor on a first surface of the substrate; and
a plastic material covering portions of the substrate and the surface mount inductor.
18. The SIP of claim 17 further comprising a thermal pad on an opposite second surface of the substrate.
19. The SIP of claim 17 , wherein the inductor includes a body portion and two end portions, the two end portions electrically connected to the substrate, the body portion offset from the two end portions defining a gap.
20. The SIP of claim 19 further comprising a third capacitor in the gap and in between the substrate and the body portion.