Granted Patent B2

US 9,215,106 · App. 14/221,968 · Granted Dec 15, 2015

Abstract

Claims (34)

1. A receiver, comprising:

a first set of time-interleaved track-and-hold circuits configured to sample an input signal according to a first set of phase-shifted clock signals;

a first estimation module configured to estimate a value held at each of the first set of time-interleaved track-and-hold circuits to produce a first set of estimated data bits;

a second set of time-interleaved track-and-hold circuits configured to sample the input signal according to a second set of phase-shifted clock signals, wherein the second set of phase-shifted clock signals is the first set of phase-shifted clock signals shifted by a predetermined phase shift unit; and

a second estimation module configured to produce a second set of estimated data bits based on a value held at each of the second set of time-interleaved track-and-hold circuits, the first set of estimated data bits and at least one pre-cursor coefficient.

2. The receiver of claim 1 , wherein the second set of phase-shifted clock signals is the first set of phase-shifted clock signals shifted by one phase shift unit.

3. The receiver of claim 1 , wherein the first estimation module is a simple slicer.

4. The receiver of claim 1 , wherein the first estimation module is a 1-tap decision feedback equalizer.

5. The receiver of claim 1 , wherein the receiver is a serializer-deserializer receiver.

6. The receiver of claim 5 , wherein output signals from the receiver are provided as input signals to a clock and data recovery block.

7. The receiver of claim 6 , wherein the clock and data recovery block is a baud-rate clock and data recovery block.

8. A communication apparatus, comprising:

a first estimation module configured to sample an input signal to produce a first set of estimated data bits; and

a second estimation module configured to sample the input signal phase shifted by a predetermined phase shift unit to produce a second set of estimated data bits, wherein the second set of estimated data bits are produced at least partially based on the first set of estimated data bits and at least one pre-cursor coefficient,

wherein the first estimation module includes a first set of time-interleaved track-and-hold circuits, the first set of time-interleaved track-and-hold circuits configured to sample the input signal according to a first set of phase-shifted clock signals, wherein the second estimation module includes a second set of time-interleaved track-and-hold circuits, the second set of time-interleaved track-and-hold circuits configured to sample the input signal according to a second set of phase-shifted clock signals, and wherein the second set of phase-shifted clock signals is the first set of phase-shifted clock signals shifted by the predetermined phase shift unit.

9. The apparatus of claim 8 , wherein the second set of phase-shifted clock signals is the first set of phase-shifted clock signals shifted by one phase shift unit.

10. The apparatus of claim 8 , wherein the second set of estimated data bits is provided as input signals to a clock and data recovery block.

11. The apparatus of claim 8 , wherein the first estimation module and the second estimation module are integrated components of at least one of: a receiver and a transceiver.

12. The apparatus of claim 8 , wherein the first estimation module and the second estimation module are integrated components of at least one of: a serializer-deserializer receiver and a serializer-deserializer transceiver.

13. The apparatus of claim 8 , wherein the first estimation module includes a simple slicer.

14. The apparatus of claim 8 , wherein the first estimation module includes a 1-tap decision feedback equalizer.

15. The apparatus of claim 8 , further comprising:

a third estimation module configured to sample the input signal further phase shifted by the predetermined phase shift unit to produce a third set of estimated data bits, wherein the third set of estimated data bits are produced at least partially based on the second set of estimated data bits and at least one pre-cursor coefficient.

16. A method for correcting intersymbol interference, the method comprising:

sampling an input signal utilizing a first set of track-and-hold circuits time-interleaved based on a first set of phase-shifted clock signals;

estimating a value held at each of the first set of time-interleaved track-and-hold circuits to produce a first set of estimated data bits;

sampling the input signal utilizing a second set of track-and-hold circuits time-interleaved based on a second set of phase-shifted clock signals, wherein the second set of phase-shifted clock signals is the first set of phase-shifted clock signals shifted by a predetermined phase shift unit; and

producing a second set of estimated data bits based on a value held at each of the second set of time-interleaved track-and-hold circuits, the first set of estimated data bits and at least one pre-cursor coefficient.

17. The method of claim 16 , wherein estimated value {circumflex over (x)}′ k of a particular data bit k in the second set of estimated data bits {{circumflex over (x)}′} is produced at least partially based on estimated value {circumflex over (x)} k+1 of a subsequent data bit k+1 in the first set of estimated data bits {{circumflex over (x)}} and the at least one pre-cursor coefficient.

18. The method of claim 16 , wherein the second set of phase-shifted clock signals is the first set of phase-shifted clock signals shifted by one phase shift unit.

19. The method of claim 16 , wherein the first set of estimated data bits is estimated utilizing at least one of: a simple slicer and a 1-tap decision feedback equalizer.

20. The method of claim 16 , further comprising:

sampling the input signal utilizing a third set of track-and-hold circuits time-interleaved based on a third set of phase-shifted clock signals, wherein the third set of phase-shifted clock signals is the second set of phase-shifted clock signals further shifted by the predetermined phase shift unit; and

producing a third set of estimated data bits based on a value held at each of the third set of time-interleaved track-and-hold circuits, the second set of estimated data bits and at least one pre-cursor coefficient.

Assignments (8)