Manufacturer self-test for solid-state drives

1. An apparatus comprising:

a memory configured to store data; and

a controller configured to:

process a plurality of input/output requests to a plurality of blocks of the memory that are not marked as bad on a block list and

perform a plurality of scans on the plurality of blocks of the memory,

wherein the plurality of scans are configured to identify respective blocks of the scanned blocks as bad in response to each of:

an erase failure of the respective blocks and

a successful erase followed by a program failure of the respective blocks,

perform a code rate test that

programs the plurality of blocks during the plurality of scans at three or more code rates of an error correction code (ECC) scheme;

the plurality of scans are utilized by the controller with each of three or more scans at an end of the plurality of scans utilizing a different one of the three or more code rates, and

mark any of the plurality of blocks identified as bad on the block list;

wherein the code rate test is initiated independent of the erase failure and the program failure.

2. The apparatus according to claim 1 , wherein the plurality of scans implement a manufacturer self-test performed prior to processing the plurality of input/output requests.

3. The apparatus according to claim 1 , wherein the three or more code rates of the code rate test in the plurality of scans are arranged in a plurality of tiers in an adaptive code rate technique used by the controller to process the plurality of input/output requests, and at least one of the plurality of tiers includes at least two of the code rates.

4. The apparatus according to claim 3 , wherein the code rate test checks the code rates utilized by the controller instead of predicting code rates in each of the plurality of blocks.

5. The apparatus according to claim 3 , wherein the code rate test is performed in a manufacturer self-test prior to processing the plurality of input/output requests, and initializes a code rate table used by the controller to process the plurality of input/output requests.

6. The apparatus according to claim 3 , wherein the code rate test is conducted in a last few rounds of the plurality of scans that are less than all of the plurality of scans.

7. The apparatus according to claim 3 , wherein the code rate test is configured to stop at an intermediate code rate of the three or more code rates based on a number of decoding iterations.

8. The apparatus according to claim 3 , wherein the code rate test includes a low-density parity-check code to program the plurality of blocks.

9. The apparatus according to claim 8 , wherein a failure criteria of the code rate test is a hard-decision low-density parity-check failure in a first mode, and an average number of decoding iterations performed on the respective blocks during the code rate test in a second mode.

10. The apparatus according to claim 1 , wherein the plurality of scans are performed in parallel on multiple blocks in multiple planes of the memory.

11. The apparatus according to claim 10 , wherein one of the plurality of scans is performed on a single block of the memory in a respective one of the multiple planes in response to a failure detected by the plurality of scans that are performed in parallel on the multiple blocks in the multiple planes.

12. The apparatus according to claim 1 , wherein a time taken to perform the plurality of scans is consistent among multiple copies of the apparatus, and the apparatus reduces a test time of the plurality of scans.

13. The apparatus according to claim 1 , wherein the plurality of scans are performed in a manufacturer self-test prior to processing the plurality of input/output requests, and the plurality of scans initialize the block list used by the controller to process the plurality of input/output requests.

14. The apparatus according to claim 1 , wherein the block list has a single-plane block level granularity.

15. The apparatus according to claim 1 , wherein the controller is configured to implement a 2-tier code rate adaptation technique to process the plurality of input/output requests, and support up to five of the code rates.

16. The apparatus according to claim 1 , wherein the controller and the memory are part of a solid state drive.

17. A method for scanning with a controller, comprising the steps of:

processing a plurality of input/output requests to a plurality of blocks of a memory that are not marked as bad on a block list; and

performing a plurality of scans on the plurality of blocks of the memory with the controller,

wherein the plurality of scans are configured to identify respective blocks of the scanned blocks as bad in response to each of:

an erase failure of the respective blocks and

a successful erase followed by a program failure of the respective blocks,

performing a code rate test that

programs the plurality of blocks during the plurality of scans at three or more code rates of an error correction code (ECC) scheme;

the plurality of scans are utilized by the controller with each of three or more scans at an end of the plurality of scans utilizing a different one of the three or more code rates, and

mark any of the plurality of blocks identified as bad on the block list;

wherein the code rate test is initiated independent of the erase failure and the program failure.

18. An apparatus comprising:

an interface configured to process a plurality of read/write operations to/from a memory; and

a control circuit configured to:

process a plurality of input/output requests to a plurality of blocks of the memory that are not marked as bad on a block list and

perform a plurality of scans on the plurality of blocks of the memory,

wherein the plurality of scans are configured to identify respective blocks of the scanned blocks as bad in response to each of:

an erase failure of the respective blocks and

a successful erase followed by a program failure of the respective blocks,

perform a code rate test that

programs the plurality of blocks during the plurality of scans at three or more code rates of an error correction code (ECC) scheme;

the plurality of scans are utilized by the control circuit with each of three or more scans at an end of the plurality of scans utilizing a different one of the three or more code rates, and

mark any of the plurality of blocks identified as bad on the block list;

wherein the code rate test is initiated independent of the erase failure and the program failure.

19. The apparatus according to claim 18 , wherein the interface and the control circuit are part of a solid-state drive controller.

20. The method according to claim 17 , wherein the memory and the controller are part of a solid-state drive.