Peak to average power ratio suppression
View Patent ↗A transmitter may comprise a first domain translation circuit, a first PAPR suppression circuit, and a descriptor generation circuit. The first domain translation circuit may convert a plurality of frequency-domain symbols of a first OFDM symbol to a corresponding plurality of first time-domain signals. The first PAPR suppression circuit may group the plurality of first time-domain signals into a plurality of sub-bands of the first time-domain. The first PAPR suppression circuit may invert one or more of the sub-bands of the first time-domain signals according to a value of a first descriptor. The descriptor generation circuit may determine the value of the first descriptor using an iterative process in which each iteration comprises random selection of a value of the first descriptor, determination of a PAPR of the first OFDM symbol processed using the randomly-selected value, and determination of whether said PAPR meets one or more determined criteria.
1. A system comprising:
a first domain translation circuit, a first peak-to-average-power ratio (PAPR) suppression circuit, and a descriptor generation circuit, wherein:
said first domain translation circuit is operable to convert a plurality of frequency-domain symbols to a corresponding plurality of first time-domain signals;
said first PAPR suppression circuit is operable to:
group said plurality of first time-domain signals into a plurality of sub-bands of said plurality of first time-domain signals; and
invert one or more of said sub-bands of said plurality of first time-domain signals according to a value of a first descriptor received from said descriptor generation circuit; and
said descriptor generation circuit comprises one or more second domain translation circuits and is operable to determine said value of said first descriptor using an iterative process in which each iteration comprises:
random selection of a value of said first descriptor;
determination of a PAPR of said plurality of first time-domain signals processed using said randomly-selected value of said first descriptor; and
determination of whether said PAPR meets one or more determined criteria.
2. The system of claim 1 , wherein said one or more second domain translation circuits are lower resolution than said first domain translation circuits.
3. The system of claim 1 , wherein, as part of said determination of said PAPR of said plurality of first time-domain signals processed using said randomly-selected value of said first descriptor, said descriptor generation circuit is operable to:
translate said plurality of frequency-domain symbols corresponding to said plurality of first time-domain signals into a plurality of second time-domain signals; and
group said plurality of second time-domain signals into a plurality of sub-bands of said plurality of second time-domain signals.
4. The system of claim 3 , wherein, as part of said determination of said PAPR of said plurality of first time-domain signals processed using said randomly-selected value of said first descriptor, said descriptor generation circuit is operable to invert one or more of said sub-bands of said plurality of second time-domain signals according to said randomly-selected value of said first descriptor.
5. The system of claim 4 , wherein, as part of said determination of said PAPR of said plurality of first time-domain signals processed using said randomly-selected value of said first descriptor, said descriptor generation circuit is operable to:
combine said sub-bands of said plurality of second time-domain signals into a combined signal; and
measure a PAPR of said combined signal.
6. The system of claim 1 , wherein said one or more determined criteria comprise said PAPR being below a determined threshold.
7. The system of claim 1 , wherein said first domain translation circuit is an inverse-fast-Fourier-transform circuit.
8. The system of claim 1 , comprising:
a second domain translation circuit and a second peak-to-average-power ratio (PAPR) suppression circuit, wherein:
said second domain translation circuit is operable to convert a plurality of frequency-domain symbols corresponding to a plurality of second time-domain signals to a corresponding plurality of third time-domain signals;
said second PAPR suppression circuit is operable to:
group said plurality of third time-domain signals into a plurality of sub-bands of said plurality of third time-domain signals; and
invert one or more of said sub-bands of said plurality of third time-domain signals according to a value of a second descriptor received from said descriptor generation circuit.
9. The system of claim 8 , comprising:
a combiner circuit operable to combine an output of said first PAPR suppression circuit and an output of said second PAPR suppression circuit;
a digital-to-analog converter (DAC) operable to convert an output of said combiner to an analog representation; and
a front-end operable to transmit an output of said DAC onto a communication medium.
10. A system comprising:
a first domain translation circuit, a first peak-to-average-power ratio (PAPR) suppression circuit, and a descriptor generation circuit, wherein:
said first domain translation circuit is operable to convert a plurality of frequency-domain symbols to a corresponding plurality of first time-domain signals;
said first PAPR suppression circuit is operable to:
group said plurality of first time-domain signals into a plurality of sub-bands of said plurality of first time-domain signals; and
invert one or more of said sub-bands of said plurality of first time-domain signals according to a value of a first descriptor received from said descriptor generation circuit;
said descriptor generation circuit is operable to determine said value of said first descriptor using an iterative process in which each iteration comprises:
random selection of a value of said first descriptor;
determination of a PAPR of said plurality of time-domain signals processed using said randomly-selected value of said first descriptor; and
determination of whether said PAPR meets one or more determined criteria; and
as part of said determination of said PAPR of said plurality of first time-domain signals processed using said randomly-selected value of said first descriptor, said descriptor generation circuit is operable to:
translate said plurality of frequency-domain symbols corresponding to said plurality of first time-domain signals into a plurality of second time-domain signals; and
group said plurality of second time-domain signals into a plurality of sub-bands of said plurality of second time-domain signals.
11. The system of claim 10 , wherein, as part of said determination of said PAPR of said plurality of first time-domain signals processed using said randomly-selected value of said first descriptor, said descriptor generation circuit is operable to invert one or more of said sub-bands of said plurality of second time-domain signals according to said randomly-selected value of said first descriptor.
12. The system of claim 11 , wherein, as part of said determination of said PAPR of said plurality of first time-domain signals processed using said randomly-selected value of said first descriptor, said descriptor generation circuit is operable to:
combine said sub-bands of said plurality of second time-domain signals into a combined signal; and
measure a PAPR of said combined signal.
13. The system of claim 10 , wherein said one or more determined criteria comprise said PAPR being below a determined threshold.
14. The system of claim 10 , wherein said first domain translation circuit is an inverse-fast-Fourier-transform circuit.
15. The system of claim 10 , comprising:
a second domain translation circuit and a second peak-to-average-power ratio (PAPR) suppression circuit, wherein:
said second domain translation circuit is operable to convert a plurality of frequency-domain symbols corresponding to a plurality of second time-domain signals to a corresponding plurality of third time-domain signals; and
said second PAPR suppression circuit is operable to:
group said plurality of third time-domain signals into a plurality of sub-bands of said plurality of third time-domain signals; and
invert one or more of said sub-bands of said plurality of third time-domain signals according to a value of a second descriptor received from said descriptor generation circuit.
16. The system of claim 15 , comprising:
a combiner circuit operable to combine an output of said first PAPR suppression circuit and an output of said second PAPR suppression circuit;
a digital-to-analog converter (DAC) operable to convert an output of said combiner to an analog representation; and
a front-end operable to transmit an output of said DAC onto a communication medium.
17. A system comprising:
a first domain translation circuit, a second domain translation circuit, a first peak-to-average-power ratio (PAPR) suppression circuit, a second peak-to-average-power ratio (PAPR) circuit, and a descriptor generation circuit, wherein:
said first domain translation circuit is operable to convert a plurality of frequency-domain symbols to a corresponding plurality of first time-domain signals;
said first PAPR suppression circuit is operable to:
group said plurality of first time-domain signals into a plurality of sub-bands of said plurality of first time-domain signals; and
invert one or more of said sub-bands of said plurality of first time-domain signals according to a value of a first descriptor received from said descriptor generation circuit; and
said descriptor generation circuit is operable to determine said value of said first descriptor using an iterative process in which each iteration comprises:
random selection of a value of said first descriptor;
determination of a PAPR of said plurality of first time-domain signals processed using said randomly-selected value of said first descriptor; and
determination of whether said PAPR meets one or more determined criteria;
said second domain translation circuit is operable to convert a plurality of frequency-domain symbols corresponding to a plurality of second time-domain signals to a corresponding plurality of third time-domain signals; and
said second PAPR suppression circuit is operable to:
group said plurality of third time-domain signals into a plurality of sub-bands of said plurality of third time-domain signals; and
invert one or more of said sub-bands of said plurality of third time-domain signals according to a value of a second descriptor received from said descriptor generation circuit.
18. The system of claim 17 , wherein said descriptor generation circuit comprises one or more second domain translation circuits.
19. The system of claim 18 , wherein said one or more second domain translation circuits are lower resolution than said first domain translation circuits.
20. The system of claim 17 , wherein, as part of said determination of said PAPR of said first plurality of time-domain signals processed using said randomly-selected value of said first descriptor, said descriptor generation circuit is operable to:
translate said plurality of frequency-domain symbols of said plurality of first time-domain signals into a plurality of second time-domain signals; and
group said plurality of second time-domain signals into a plurality of sub-bands of said plurality of second time-domain signals.
21. The system of claim 20 , wherein, as part of said determination of said PAPR of said plurality of first time-domain signals processed using said randomly-selected value of said first descriptor, said descriptor generation circuit is operable to invert one or more of said sub-bands of said plurality of second time-domain signals according to said randomly-selected value of said first descriptor.
22. The system of claim 21 , wherein, as part of said determination of said PAPR of said plurality of first time-domain signals processed using said randomly-selected value of said first descriptor, said descriptor generation circuit is operable to:
combine said sub-bands of said plurality of second time-domain signals into a combined signal; and
measure a PAPR of said combined signal.
23. The system of claim 17 , wherein said one or more determined criteria comprise said PAPR being below a determined threshold.
24. The system of claim 17 , wherein said first domain translation circuit is an inverse-fast-Fourier-transform circuit.
25. The system of claim 24 , comprising:
a combiner circuit operable to combine an output of said first PAPR suppression circuit and an output of said second PAPR suppression circuit;
a digital-to-analog converter (DAC) operable to convert an output of said combiner to an analog representation; and
a front-end operable to transmit an output of said DAC onto a communication medium.