Methods of forming transistor gates
View Patent ↗Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at least some portions of the different types of gates. FET and charge storage transistor gate stacks may be formed. The gate stacks may each include a gate material, an insulative material, and a sacrificial material. The sacrificial material is removed from the FET and charge storage transistor gate stacks. The insulative material of the FET gate stacks is etched through. A conductive material is formed over the FET gate stacks and over the charge storage transistor gate stacks. The conductive material physically contacts the gate material of the FET gate stacks, and is separated from the gate material of the charge storage transistor gate stacks by the insulative material remaining in the charge storage transistor gate stacks. Some embodiments include gate structures.
1. A method of forming a field effect transistor (FET) gate, comprising:
forming a gate stack over a semiconductor substrate; the gate stack comprising a gate dielectric material, a first silicon-containing material over the gate dielectric material, three discrete electrically insulative materials over the first silicon-containing material and stacked directly atop one another, and a second silicon-containing material over the electrically insulative materials, the second silicon-containing material comprising amorphous silicon;
removing the second silicon-containing material selectively relative to an uppermost one of the three discrete electrically insulative materials;
etching through all of the three discrete electrically insulative materials to form an opening that extends through the electrically insulative materials to expose the first silicon-containing material; and
forming an electrically conductive material within said opening and in physical contact with the first silicon-containing material;
wherein at least one of the three discrete electrically insulative materials comprises at least one of the following materials: hafnium; aluminum and zirconium; and
wherein the removing of the second silicon-containing material forms a cavity over the three discrete electrically insulative materials, and wherein the etching of the three discrete electrically insulative materials removes beneath the cavity.
2. The method of claim 1 wherein the first silicon-containing material is conductively doped.
3. The method of claim 1 wherein the second silicon-containing material is conductively doped.
4. The method of claim 1 wherein the electrically conductive material comprises one or more metals.
5. The method of claim 1 wherein the electrically conductive material comprises one or more metal nitride compositions.
6. The method of claim wherein the first and second silicon-containing materials are conductively doped; and wherein the electrically conductive material comprises one or more metal nitride compositions.
7. The method of claim 1 wherein the electrically conductive material directly contacts ail of the three discrete electrically insulative materials.
8. The method of claim 1 further comprising forming an insulative spacer against at least a portion of the gate stack.
9. The method of claim 1 further comprising forming a spacer against at least a plurality of structures of the gate stack.
10. The method of claim 1 wherein the second silicon-containing material is not conductively doped.
11. The method of claim 1 wherein the at least one of the three discrete electrically insulative materials comprises at least two of the following materials: hafnium; aluminum and zirconium.
12. The method of claim 1 wherein the at least one of the three discrete electrically insulative materials comprises zirconium.
13. The method of claim 1 wherein the second silicon-containing material comprises both amorphous and polycrystalline silicon.
14. A method of forming a field effect transistor (FET) gate, comprising:
forming a gate stack over a semiconductor substrate; the gate stack comprising a gate dielectric material, a first silicon-containing material over the gate dielectric material, an electrically insulative material over the first silicon-containing material, and a second silicon-containing material over the electrically insulative material;
removing the second silicon-containing material to the electrically insulative material, the removing comprising removing an entirety of the second silicon-containing material over the electrically insulative material;
etching the electrically insulative material to form an opening that extends through the electrically insulative material to expose the first silicon-containing material; and
forming an electrically conductive material within said opening and in physical contact with the first silicon-containing material.
15. The method of claim 14 wherein the electrically conductive material is a first electrically conductive material, and further comprising forming a second electrically conductive material against the first electrically conductive material.
16. The method of claim 15 wherein the first and second electrically conductive materials fill the opening.
17. The method of claim 14 wherein the etching comprises etching only the electrically insulative material to expose the first silicon-containing material.
18. The method of claim 14 wherein the electrically insulative material comprises zirconium.
19. The method of claim 14 wherein the second silicon-containing material comprises both amorphous and polycrystalline silicon.
20. The method of claim 14 wherein the second silicon-containing material comprises amorphous silicon.
21. The method of claim 14 wherein the removing of the second silicon-containing material forms a cavity over the electrically insulative material, and wherein the etching of the electrically insulative material removes only a portion of the electrically insulative material from beneath the cavity.
22. A method of forming a field effect transistor (FET) gate, comprising:
forming a gate stack over a semiconductor substrate; the gate stack comprising a gate dielectric material, a first silicon-containing material over the gate dielectric material, an electrically insulative material over the first silicon-containing material, and a second silicon-containing material over the electrically insulative material;
removing the second silicon-containing material to the electrically insulative material;
etching the electrically insulative material to form an opening that extends through the electrically insulative material to expose the first silicon-containing material;
forming an electrically conductive material within said opening and in physical contact with only two structures of the following four structures: gate dielectric material, the first silicon-containing material, the electrically insulative material, and/or the second silicon-containing material; and
wherein the removing of the second silicon-containing material forms a cavity over the electrically insulative material, and wherein the etching the electrically insulative material remove only a portion of the electrically insulative material from beneath the cavity.
23. The method of claim 22 wherein the electrically conductive material is a first electrically conductive material, and further comprising forming a second electrically conductive material against the first electrically conductive material.
24. The method of claim 23 wherein the first and second electrically conductive materials fill the opening.
25. The method of claim 22 wherein the etching comprises etching only the electrically insulative material to expose the first silicon-containing material.
26. The method of claim 22 wherein the electrically insulative material comprises zirconium.
27. The method of claim 22 wherein the second silicon-containing material comprises both amorphous and polycrystalline silicon.
28. The method of claim 22 wherein the second silicon-containing material comprises amorphous silicon.