METHOD AND SYSTEM FOR A GALLIUM NITRIDE VERTICAL JFET WITH SELF-ALIGNED GATE METALLIZATION
A semiconductor device includes a III-nitride substrate and a first III-nitride epitaxial layer coupled to the III-nitride substrate and comprising a drift region, a channel region, and an extension region. The channel region is separated from the III-nitride substrate by the drift region. The channel region is characterized by a first width. The extension region is separated from the drift region by the channel region. The extension region is characterized by a second width less than the first width. The semiconductor device also includes a second III-nitride epitaxial layer coupled to a top surface of the extension region, a III-nitride gate structure coupled to a sidewall of the channel region and laterally self-aligned with respect to the extension region, and a gate metal structure in electrical contact with the III-nitride gate structure and laterally self-aligned with respect to the extension region.
1 . A semiconductor device comprising:
a III-nitride substrate;
a first III-nitride epitaxial layer coupled to the III-nitride substrate and comprising a drift region, a channel region, and an extension region, wherein:
the channel region is separated from the III-nitride substrate by the drift region, the channel region being characterized by a first width; and
the extension region is separated from the drift region by the channel region, the extension region being characterized by a second width less than the first width;
a second III-nitride epitaxial layer coupled to a top surface of the extension region;
a III-nitride gate structure coupled to a sidewall of the channel region and laterally self-aligned with respect to the extension region; and
a gate metal structure in electrical contact with the III-nitride gate structure and laterally self-aligned with respect to the extension region.
2 . The semiconductor device of claim 1 wherein the gate metal structure is laterally self-aligned with respect to a sidewall of the extension region.
3 . The semiconductor device of claim 3 wherein the gate metal structure is characterized by a lateral width equal to a lateral width of the III-nitride gate structure.
4 . The semiconductor device of claim 1 wherein the gate metal structure is characterized by a lateral width less than a lateral width of the III-nitride gate structure.
5 . The semiconductor device of claim 1 further comprising a dielectric layer overlying at least a portion of the III-nitride gate structure, wherein a top surface of the dielectric layer is substantially co-planar with a top surface of the extension region.
6 . The semiconductor device of claim 5 further comprising a pad metal structure coupled to the top surface of the dielectric layer and electrically coupled to the second III-nitride epitaxial material.