IP Library Granted Patent US 8,947,806
Granted Patent B1
US 8,947,806 · App. 14/225,543 · Granted Feb 3, 2015

Cross-talk compensation in array based reader systems

Inventors: Travis Roger Oenning (Rochester, MN); George Mathew (San Jose, CA)
Assignee: LSI Corporation
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Quick Facts
Patent No.
US 8,947,806
App. No.
14/225,543
Filed
Mar 26, 2014
Granted
Feb 3, 2015
Kind
B1
Examiner
DINH, TAN X
Art Unit
2688
USPC
360/39
Abstract

A method of enhancing read performance in array-reader hardware includes generating, by the array-reader hardware, a plurality of signals, according to data read from a magnetic disk, and canceling at least a portion of cross-talk in the plurality of signals to generate a plurality of corrected signals.

Claims (38)

1. A method of enhancing read performance in array-reader hardware comprising:

generating, by the array-reader hardware, a plurality of signals, according to data read from a magnetic disk; and

canceling at least a portion of cross-talk in the plurality of signals to generate a plurality of corrected signals;

wherein canceling at least the portion of the cross-talk comprises:

applying a cross-talk cancelation filter to the plurality of signals, subtracting a first portion of the cross-talk from the plurality signals; and

applying a digital finite impulse response filter to each of the plurality of signals, canceling a second portion of the cross-talk.

2. The method of claim 1 , further comprising combining the plurality of corrected signals into read data.

3. The method of claim 1 , further comprising delaying at least one of the plurality of corrected signals according to a down-track separation between a plurality of read heads of the array-reader hardware.

4. The method of claim 1 , further comprising inputting the plurality of corrected signals to an equalizer.

5. The method of claim 1 , wherein different digital finite impulse response filters are applied to different ones of the plurality of signals, each of the digital finite impulse response filters comprising a plurality of shifted taps;

further comprising:

determining a sum of tap amplitudes of the cross-talk cancelation filter; and

passing the plurality of signals unmodified when the sum of the tap amplitudes is less than a prescribed threshold.

6. The method of claim 1 , wherein canceling at least the portion of the cross-talk comprises applying a digital cross-talk cancelation filter to the plurality of signals subtracting the cross-talk from the plurality signals to generate the plurality of corrected signals.

7. The method of claim 6 , further comprising delaying at least one of the plurality of signals according to a down-track separation between a plurality of read heads of the array-reader hardware after applying the digital cross-talk cancelation filter to the plurality of signals.

8. The method of claim 6 , further comprising adapting the digital cross-talk cancelation filter to at least one time varying condition.

9. The method of claim 1 ,

wherein different digital finite impulse response filters are applied to different ones of the plurality of signals, wherein each of the digital finite impulse response filters comprises a plurality of shifted taps.

10. A storage system comprising:

an array-reader configured to generate a plurality of signals;

a digital cross-talk cancelation filter configured to subtract a first portion of cross-talk from the plurality signals and to generate a plurality of corrected signals; and

a plurality of digital finite impulse response filters configured to cancel a second portion of cross-talk from respective ones of the plurality of signals to generate the plurality of corrected signals.

11. The storage system of claim 10 , further comprising a delay circuit configured to delay at least one of the plurality of corrected signals according to a down-track separation between a plurality of read heads of the array-reader.

12. The storage system of claim 10 , further comprising an equalizer configured to reshape the plurality of corrected signals.

13. The storage system of claim 10 , further comprising a low-pass filter disposed between the array-reader and an analog-to-digital converter, wherein the analog-to-digital converter is disposed between the low-pass filter and the digital cross-talk cancelation filter.

14. The storage system of claim 10 , wherein the digital cross-talk cancelation filter is adaptive to at least one time varying condition.

15. A storage system comprising:

an array-reader configured to generate a plurality of signals; and

an equalizer comprising a plurality of digital finite impulse response filters configured to subtract cross-talk from respective ones of the plurality of signals and to generate a plurality of corrected signals;

wherein the plurality of digital finite impulse response filters is configured to adjust a delay of at least one of the plurality of signals according to a down-track separation between a plurality of read heads of the array-reader.

16. The storage system of claim 15 , wherein the equalizer is configured to reshape the plurality of signals.

17. The storage system of claim 15 , wherein the plurality of digital finite impulse response filters are adaptive to at least one time varying condition.

18. A data storage system, comprising:

a plurality of storage devices, wherein at least one of the plurality of storage devices comprises:

an array-reader configured to generate a plurality of signals; and

at least one of a digital cross-talk cancelation filter and a plurality of digital finite impulse response filters,

wherein the digital cross-talk cancelation filter is configured to subtract cross-talk from the plurality of signals and to generate a plurality of corrected signals, and the plurality of digital finite impulse response filters are configured to subtract the cross-talk from respective ones of the plurality of signals and to generate the plurality of corrected signals.

19. The data storage system of claim 18 , wherein the at least one of the plurality of storage devices is configured as a device in a redundant array of independent devices (RAID) system.

Assignments (8)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE OF THE MERGER PREVIOUSLY RECORDED ON REEL 047642 FRAME 0417. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT, Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048521/0395 →
MERGER Recorded Oct 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047642/0417 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 26, 2014
From: OENNING, TRAVIS ROGER; MATHEW, GEORGE
To: LSI CORPORATION
Reel/Frame 032526/0326 →
Continuity (1)
Provisional Application 61939192 · Feb 12, 2014