Integrated PAM4/NRZ N-Way Parallel Digital Unrolled Decision Feedback Equalizer (DFE)
An N-way parallel, unrolled decision feedback equalizer for a SerDes receiver can convert between four-tap PAM-2 and two-tap PAM-4 mode, maximizing hardware through the use of mode control multiplexers. Each of N interleaved parallel branches includes an ISI correction stage for generating a partial result approximating intersymbol interference and comparing the partial result to a threshold, a carry look-ahead stage for generating a second partial result based in part on previously generated partial results, and a decision feedback stage for generating a final decision based on previous branches. Mode control multiplexers can select from PAM-2 and PAM-4 operating modes, PAM-2 and MAP-4 inputs at various stages, or from single-bit PAM-2 and two-bit PAM-4 outputs. ISI correction can additionally be reformulated to incorporate comparing raw input symbols to a combination of approximated ISI and a threshold.
1 . A system for generating equalized output symbols by applying decision feedback equalization to received single-bit PAM-2 and two-bit PAM- 4 input symbols, comprising:
a plurality of interleaved sequential branches, each interleaved branch including
(a) a correction stage including a plurality of correction blocks, each block configured to generate a first partial result by combining the received input symbol with at least one tap, the tap generated by multiplying a previously decoded input symbol by a predetermined coefficient, and a plurality of decision devices, each decision device operably coupled to a correction block and configured to generate a first decision result by comparing the first partial result to a predetermined threshold voltage,
(b) a carry look-ahead stage configured to generate at least one second partial result based on at least one of a first decision result and a second partial result generated by a previous branch, and
(c) a decision feedback stage including at least one multiplexer configured to select a final decision result from the at least one second partial result, and
(d) at least one pipeline structure configured to store at least one of a first partial result, a first decision result, a second partial result, and a final decision result; and
at least one multiplexer configured to select at least one final decision result from a first plurality of PAM-2 final decision results and a second plurality of PAM-4 final decision results generated by the plurality of branches.
2 . The system of claim 1 , further comprising:
at least one multiplexer configured to select at least one of a PAM-2 operating mode and a PAM-4 operating mode.
3 . The system of claim 1 , further comprising:
at least one multiplexer configured to select at least one of a PAM-2 coefficient and a PAM-4 coefficient;
at least one multiplexer configured to select at least one of a first plurality of PAM-2 taps and a second plurality of PAM-4 taps.
4 . The system of claim 3 , wherein the at least one multiplexer configured to select at least one of a first plurality of PAM-2 taps and a second plurality of PAM-4 taps includes at least one multiplexer configured to select at least one of a set of four PAM-2 taps and a set of two PAM-4 taps.
5 . The system of claim 1 , wherein the system is an 8-way parallel decision feedback equalizer having 8 branches.
6 . The system of claim 1 , wherein each decision device is at least one of a comparator or a slicer.
7 . The system of claim 1 , wherein the at least one multiplexer includes a multiplexer loop.
8 . The system of claim 1 , wherein the correction stage includes
a plurality of decision devices, each decision device configured to generate a first decision result by comparing the received input symbol to a combination of a predetermined threshold voltage with at least one tap, the tap generated by multiplying a previously decoded input symbol by a predetermined coefficient.
9 . The system of claim 1 , wherein the system is embodied in a serializer/deserializer (SerDes) receiver device.
10 . A method for generating equalized output symbols by applying decision feedback equalization to received single-bit PAM-2 and two-bit PAM-4 input symbols, comprising:
selecting an operating mode from a group including PAM-2 mode and PAM-4 mode;
generating at least one first partial result by combining at least one received input symbol with at least one tap, the at least one tap generated by multiplying a previously decoded input symbol by a predetermined coefficient;
generating at least one first decision result by comparing the first partial result to a predetermined threshold voltage;
generating a plurality of second partial results based on the at least one first decision result and a previously generated second partial result; and
generating at least one final decision result based on the plurality of second partial results.
11 . The method of claim to, wherein selecting an operating mode from a group consisting of PAM-2 mode and PAM-4 mode includes selecting an operating mode from a group consisting of PAM-2 mode and PAM-4 mode via at least one multiplexer.
12 . The method of claim to, wherein selecting an operating mode from a group consisting of PAM-2 mode and PAM-4 mode includes
selecting at least one of a PAM-2 coefficient and a PAM-4 coefficient via at least one multiplexer;
selecting at least one of a first plurality of PAM-2 taps and a second plurality of PAM-4 taps via at least one multiplexer; and
selecting at least one final decision result from a first plurality of PAM-2 final decision results and a second plurality of PAM-4 decision results via at least one multiplexer.
13 . The method of claim 12 , wherein selecting at least one of a first plurality of PAM-2 taps and a second plurality of PAM-4 taps via at least one multiplexer includes selecting at least one of a set of four PAM-2 taps and a set of two PAM-4 taps via at least one multiplexer.
14 . The method of claim 10 , wherein generating at least one first decision result by comparing the first partial result to a predetermined threshold voltage includes
generating a first decision result by comparing the at least one received input symbol to a combination of a predetermined threshold voltage with at least one tap, the tap generated by multiplying at least one previously decoded input symbol by a predetermined coefficient.
15 . The method of claim 10 , wherein the method is embodied in instructions executable by at least one of a processor and a circuit operably coupled to a serializer/deserializer (SerDes) receiver.