SOI FinFET transistor with strained channel
Stress is introduced into the channel of an SOI FinFET device by transfer directly from a metal gate. In SOI devices in particular, stress transfer efficiency from the metal gate to the channel is nearly 100%. Either tensile or compressive stress can be applied to the fin channel by choosing different materials to be used in the gate stack as the bulk gate material, a gate liner, or a work function material, or by varying processing parameters during deposition of the gate or work function materials. P-gates and N-gates are therefore formed separately. Gate materials suitable for use as stressors include tungsten (W) for NFETs and titanium nitride (TiN) for PFETs. An optical planarization material assists in patterning the stress-inducing metal gates. A simplified process flow is disclosed in which isolation regions are formed without need for a separate mask layer, and gate sidewall spacers are not used.
1. A method, comprising:
forming a source region by implanting ions in a layer of a substrate through a hard mask, the layer being on a buried oxide layer in the substrate, the ions being above the buried oxide layer;
forming a drain region by implanting ions in the layer through the hard mask, the ions being above the buried oxide layer;
forming a fin that extends between the source region and the drain region;
forming a stress-inducing metal gate on the fin;
forming an insulating layer overlying the stress-inducing metal gate; and
forming contact openings in the insulating layer.
2. The method of claim 1 , further including:
forming isolation trenches; and
forming a gate dielectric and filling the isolation trenches during one film deposition processing step.
3. The method of claim 2 , wherein forming the fin and forming the isolation trenches occur during one etch processing step.
4. The method of claim 1 , further comprising forming an interconnect layer and coupling the interconnect layer to at least the stress-inducing metal gate by filling the contact openings.
5. The method of claim 1 , wherein forming the stress-inducing metal gate includes depositing and patterning a stress-inducing metal film.
6. The method of claim 5 , wherein forming the stress-inducing metal gate further includes depositing an optical planarization material on the stress-inducing metal film.
7. The method of claim 1 wherein the hard mask is used to form the source and drain regions and the fin.
8. The method of claim 1 , wherein forming the stress-inducing metal gate does not include using a replacement gate.
9. The method of claim 2 , wherein the gate dielectric is a high-k material having a dielectric constant greater than about 4.0.
10. A method, comprising:
forming a source region of an n-type transistor by implanting negative ions in a silicon substrate, a lower boundary of the source region corresponding to a top surface of a buried oxide layer in the silicon substrate;
forming a drain region of the n-type transistor by implanting negative ions in the silicon substrate, a lower boundary of the drain region corresponding to the top surface of the buried oxide layer;
forming a fin extending away from a surface of the silicon substrate, the fin extending between the source region and the drain region;
covering the fin with a gate dielectric; and
forming a metal gate in contact with the gate dielectric, the metal gate inducing a tensile stress in the fin.
11. The method of claim 10 , wherein the metal gate includes a single tungsten layer that induces the tensile stress in the fin.
12. The method of claim 11 , wherein forming the metal gate includes applying an optical planarization layer on top of the single tungsten layer.
13. The method of claim 10 , wherein the metal gate is formed by a deposition process in which a process parameter is adjusted according to tensile stress measurements of the fin.
14. The method of claim 13 wherein the tensile stress measurements are performed during the deposition process.
15. A method, comprising:
forming a source region of a p-type transistor by implanting positive ions in a silicon substrate to a lower implant depth determined by an interface between a silicon layer on a buried oxide layer and the buried oxide layer;
forming a drain region of the p-type transistor by implanting positive ions in the silicon substrate to the lower implant depth determined by the interface between the silicon layer and the buried oxide layer;
forming a fin extending away from a surface of the silicon substrate, the fin extending between the source region and the drain region;
covering the fin with a gate dielectric; and
forming a metal gate in contact with the gate dielectric, the metal gate inducing a compressive stress in the fin.
16. The method of claim 15 , wherein the metal gate includes a tungsten layer on a titanium nitride layer that induces the compressive stress in the fin.
17. The method of claim 16 , wherein forming the metal gate includes applying an optical planarization layer on the tungsten layer.
18. The method of claim 15 , wherein the metal gate is formed by a deposition process in which a process parameter is adjusted according to compressive stress measurements of the fin.
19. The method of claim 18 wherein the compressive stress measurements are performed during the deposition process.