Cell processing method and device for switch fabric chip
View Patent ↗A cell processing method and device for a Switch Fabric (SF) chip are disclosed, which belong to the field of communications. The SF chip includes a unicast route table, which is multiplexed in two working modes and is looked up according to a unicast cell, and a multicast route table, which is multiplexed in the two working modes and is looked up according to a multicast cell. The cell processing method for an SF chip includes: the SF chip receives a cell and an input link number corresponding to the cell from an upstream apparatus and extracts a destination Identifier (ID) of the cell; the SF chip looks up a route table according to a working mode of the SF chip, the destination ID and the input link number to determine a first bitmap corresponding to the cell; and the SF chip performs load balancing on the first bitmap to obtain a second bitmap and outputs the cell to a downstream apparatus according to the second bitmap. With the technical solutions of the disclosure, the SF chip in a cascade switching system can adapt to different working modes.
1. A cell processing method for a Switch Fabric SF chip, comprising:
providing, in the SF chip, a unicast route table, which is multiplexed in two working modes of an SF13 mode and an SF2 mode and is looked up according to a unicast cell;
providing, in the SF chip, a multicast route table, which is multiplexed in the two working modes of the SF13 mode and the SF2 mode and is looked up according to a multicast cell;
receiving, by the SF chip, a cell and an input link number corresponding to the cell from an upstream apparatus, and extracting a destination Identifier ID of the cell;
looking up, by the SF chip, a route table according to a working mode of the SF chip, the destination ID and the input link number, and determining a first bitmap corresponding to the cell; and
performing, by the SF chip, load balancing on the first bitmap to obtain a second bitmap, and outputting the cell to a downstream apparatus according to the second bitmap.
2. The method according to claim 1 , wherein when the cell is a multicast cell, the destination ID of the multicast cell is a multicast ID, and the step of looking up, by the SF chip, a route table according to a working mode of the SF chip, the destination ID and the input link number, and determining a first bitmap corresponding to the cell comprises:
looking up, by the SF chip, an SF1 multicast route table according to the multicast ID of the cell to determine a multicast bitmap with a bit width of 48 bits when the working mode of the SF chip currently is the SF13 mode and the input link number corresponds to an SF1 mode;
looking up, by the SF chip, an SF3 multicast route table according to the multicast ID of the cell to determine a multicast bitmap with a bit width of 48 bits when the working mode of the SF chip currently is the SF13 mode and the input link number corresponds to an SF3 mode; and
looking up, by the SF chip, an SF2 multicast route table according to the multicast ID of the cell to determine a multicast bitmap with a bit width of 96 bits when the working mode of the SF chip currently is the SF2 mode.
3. The method according to claim 2 , wherein the step of performing, by the SF chip, load balancing on the first bitmap to obtain the second bitmap and outputting the cell to the downstream apparatus according to the second bitmap comprise:
replacing, by the SF chip, ones in the first bitmap by zeros according to a back pressure condition of an output link;
selecting, by the SF chip in a polling way, an output link from available output links corresponding to each trunk group in the first bitmap in which ones are replaced by zeros, to obtain the second bitmap in which the available output links are equal to trunk groups in number; and
replicating, by the SF chip, the multicast cell, and outputting a plurality of replicated multicast cells to the downstream apparatus according to the second bitmap.
4. The method according to claim 1 , wherein when the cell is a unicast cell, the destination ID of the unicast cell is a unicast ID, and the step of looking up, by the SF chip, a route table according to a working mode of the SF chip, the destination ID and the input link number, and determining the first bitmap corresponding to the cell comprises:
looking up, by the SF chip, an SF1 unicast route table according to the unicast ID of the cell to determine a unicast bitmap with a bit width of 48 bits when the working mode of the SF chip currently is the SF13 mode and the input link number corresponds to an SF1 mode;
looking up, by the SF chip, an SF3 unicast route table according to the unicast ID of the cell to determine a unicast bitmap with a bit width of 48 bits when the working mode of the SF chip currently is the SF13 mode and the input link number corresponds to an SF3 mode; and
looking up, by the SF chip, an SF2 unicast route table according to the unicast ID of the cell to determine a unicast bitmap with a bit width of 96 bits when the working mode of the SF chip currently is the SF2 mode.
5. The method according to claim 4 , wherein the step of performing, by the SF chip, load balancing on the first bitmap to obtain the second bitmap and outputting the cell to the downstream apparatus according to the second bitmap comprise:
replacing, by the SF chip, ones in the first bitmap by zeros according to a back pressure condition of the output link; and
selecting, by the SF chip in a polling way, an output link from all available output links in the first bitmap in which ones are replaced by zeros, and outputting the unicast cell to the downstream apparatus through the output link.
6. A cell processing device for a Switch Fabric SF chip, wherein the SF chip comprises: a unicast route table, which is multiplexed in two working modes and is looked up according to a unicast cell, and a multicast route table, which is multiplexed in the two working modes and is looked up according to a multicast cell, the two working modes are an SF13 mode and an SF2 mode, and the cell processing device for an SF chip comprises:
a memory configured to store instructions, when executed by a processor, the instructions being configured to
receive a cell and an input link number corresponding to the cell from an upstream apparatus and extract a destination Identifier ID of the cell;
look up a route table according to a working mode of the SF chip, the destination ID and the input link number, and determine a first bitmap corresponding to the cell;
perform load balancing on the first bitmap to obtain a second bitmap; and
output the cell to a downstream apparatus according to the second bitmap.
7. The device according to claim 6 , wherein when the cell is a multicast cell, the destination ID of the multicast cell is a multicast ID; and
the instructions are further configured to:
look up an SF1 multicast route table according to the multicast ID of the cell, and determine a multicast bitmap with a bit width of 48 bits when the working mode of the SF chip currently is the SF13 mode and the input link number corresponds to an SF1 mode;
look up an SF3 multicast route table according to the multicast ID of the cell to determine a multicast bitmap with a bit width of 48 bits when the working mode of the SF chip currently is the SF13 mode and the input link number corresponds to an SF3 mode; and
look up an SF2 multicast route table according to the multicast ID of the cell to determine a multicast bitmap with a bit width of 96 bits when the working mode of the SF chip currently is the SF2 mode.
8. The device according to claim 7 , wherein
the instructions are further configured to replace ones in the first bitmap by zeros according to a back pressure condition of an output link and select, in a polling way, an output link from available output links corresponding to each trunk group in the first bitmap in which ones are replaced by zeros, to obtain the second bitmap in which the available output links are equal to trunk groups in number; and
the instructions are further configured to replicate the multicast cell and output a plurality of replicated multicast cells to the downstream apparatus according to the second bitmap.
9. The device according to claim 6 , wherein when the cell is a unicast cell, the destination ID of the unicast cell is a unicast ID; and
the instructions are further configured to:
look up an SF1 unicast route table according to the unicast ID of the cell to determine a unicast bitmap with a bit width of 48 bits when the working mode of the SF chip currently is the SF13 mode and the input link number corresponds to an SF1 mode;
look up an SF3 unicast route table according to the unicast ID of the cell to determine a unicast bitmap with a bit width of 48 bits when the working mode of the SF chip currently is the SF13 mode and the input link number corresponds to an SF3 mode; and
look up an SF2 unicast route table according to the unicast ID of the cell to determine a unicast bitmap with a bit width of 96 bits when the working mode of the SF chip currently is the SF2 mode.
10. The device according to claim 9 , wherein
the instructions are further configured to replace ones in the first bitmap by zeros according to a back pressure condition of the output link and select, in a polling way, an output link from all available output links in the first bitmap in which ones are replaced by zeros; and
the instructions are further configured to output the unicast cell to the downstream apparatus through the output link.