IP Library Granted Patent US 9,405,614
Granted Patent B2
US 9,405,614 · App. 14/233,230 · Granted Aug 2, 2016

Method and system for reducing write-buffer capacities within memristor-based data-storage devices

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Quick Facts
Patent No.
US 9,405,614
App. No.
14/233,230
Granted
Aug 2, 2016
Kind
B2
Abstract

One example disclosed in the application is an electronic data-storage device comprising one or more arrays of memory elements. The data-storage device also includes an error-control-coding encoder that encodes received data and a READ/WRITE controller that writes encoded data received from the error-control-coding encoder to a number of memory elements by applying the switching-inducing force or gradient to the one or more arrays of memory elements until more than a maximum-allowed number of WRITE requests have been queued to the WRITE-request buffer, until feedback signals indicate that the WRITE operation has completed, or until the switching-inducing force or gradient has been applied for a maximum application time.

Claims (28)

1. A data-storage device comprising:

one or more arrays of memory elements that each includes

a material that switches between at least two different states by application of a switching-inducing force or gradient to the material, and

a feedback signal;

a WRITE-request buffer that buffers a received WRITE request;

an error-control-coding encoder that encodes data associated with the WRITE request; and

a READ/WRITE controller that writes the data, encoded by the error-control-coding encoder, associated with the WRITE request received from the WRITE-request buffer, to a number of memory elements by applying the switching-inducing force or gradient to the one or more arrays of memory elements until more than a maximum-allowed number of WRITE requests have been queued to the WRITE-request buffer, feedback signals indicate that the WRITE operation has completed, or the switching-inducing force or gradient has been applied for a maximum application time.

2. The data-storage device of claim 1 wherein the memory elements are characterized by log-normally-distributed switching times.

3. The data-storage device of claim 1 wherein the maximum application time is shorter than a time that would provide a specified bit error rate for uncoded WRITE operations.

4. The data-storage device of claim 3 further including an error-control-coding decoder that decodes data read from the one or more arrays of memory elements by the READ/WRITE controller.

5. The data-storage device of claim 1 wherein the size of the WRITE-request buffer is smaller than a WRITE-request-buffer size that would ensure that any WRITE operation corresponding to an already-received WRITE-request is not terminated prior to successful completion or application of the switching-inducing force or gradient for a maximum application time.

6. The data-storage device of claim 5 further including an error-control-coding decoder that decodes data read from the one or more arrays of memory elements by the READ/WRITE controller, in the process of decoding correcting a sufficient number of erroneous bit values to provide a specified bit error rate despite switching errors that occur as a result of termination of WRITE operations corresponding to already-received WRITE-requests that are terminated prior to successful completion or application of the switching-inducing force or gradient for a maximum application time.

7. The data-storage device of claim 1 wherein the data-storage medium is a memristive material that switches between a first resistivity state and a second resistivity state when a switching-inducing voltage is applied across the data-storage medium.

8. A method for writing data to a data-storage device that includes one or more arrays of memory elements, each including a material that is switched between at least two different states by application of a switching-inducing force or gradient to the material, and a feedback signal, the method comprising:

encoding data, by an error-control-coding encoder, associated with a received WRITE-request;

queuing the WRITE request to a WRITE-request buffer; and

writing the encoded data to a number of memory elements by applying the switching-inducing force or gradient to the one or more arrays of memory elements until more than a maximum-allowed number of WRITE requests have been queued to the WRITE-request buffer, feedback signals indicate that the WRITE operation has completed, or the switching-inducing force or gradient has been applied for a maximum application time.

9. The method of claim 8 further including selecting the maximum application time to be shorter than a minimum application time calculated to ensure a specified bit error rate for writing uncoded data to the one or more arrays but sufficiently long that, when the data is subsequently read from the one or more arrays and decoded by an error-control-coding decoder that corrects up to a certain number of bit errors in the data read from the one or more arrays, the overall bit error rate for writing data to, and reading the data back from, the data-storage device is less than or equal to the specified bit error rate.

10. The method of claim 8 further including selecting a size for the WRITE-request buffer to be smaller than a WRITE-request-buffer size that would ensure that any WRITE operation corresponding to an already-received WRITE-request is not terminated prior to successful completion or application of the switching-inducing force or gradient for a maximum application time, but sufficiently large that, when data is subsequently read from the one or more arrays and decoded by an error-control-coding decoder that corrects up to a certain number of bit errors in the data read from the one or more arrays, the overall bit error rate for writing data to, and reading the data back from, the data-storage device is less than or equal to the specified bit error rate.

11. The method of claim 8 wherein the data-storage medium is a memristive material that switches between a first resistivity state and a second resistivity state when a switching-inducing voltage is applied across the data-storage medium.

12. The method of claim 8 wherein the memory elements are characterized by log-normally-distributed switching times.

13. The method of claim 8 wherein the switching-inducing force or gradient is applied to the one or more arrays of memory elements continuously while the feedback signals are continuously monitored.

14. The method of claim 8 wherein the switching-inducing force or gradient is applied to the one or more arrays of memory elements during discrete intervals, between which the feedback signals are used to determine whether or not the data has been successfully written.

15. A data-storage device comprising:

one or more arrays of memory elements that each includes a data-storage medium that is switched between at least two different states by application of a switching-inducing force or gradient to the data-storage medium;

a WRITE-request buffer;

an error-control-coding encoder that encodes received data; and

a READ/WRITE controller that writes data encoded by the error-control-coding encoder to a number of memory elements by applying the switching-inducing force or gradient to the one or more arrays of memory elements in multiple pulses, verifying that the WRITE operation has succeeded after each pulse by a READ operation, until more than a maximum-allowed number of WRITE requests have been queued to the WRITE-request buffer, until the WRITE operation has completed, or until a maximum number of pulses have been applied.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 5, 2022
From: OT PATENT ESCROW, LLC
To: VALTRUS INNOVATIONS LIMITED
Reel/Frame 061244/0298 →
PATENT ASSIGNMENT, SECURITY INTEREST, AND LIEN AGREEMENT Recorded Jan 26, 2021
From: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP; HEWLETT PACKARD ENTERPRISE COMPANY
To: OT PATENT ESCROW, LLC
Reel/Frame 055269/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 9, 2015
From: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
To: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Reel/Frame 037079/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 30, 2014
From: SEROUSSI, GADIEL; ORDENTLICH, ERIK
To: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Reel/Frame 032568/0366 →