IP Library Granted Patent US 9,087,904
Granted Patent B2
US 9,087,904 · App. 14/236,698 · Granted Jul 21, 2015

Thin-film transistor having tapered organic etch-stopper layer

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Quick Facts
Patent No.
US 9,087,904
App. No.
14/236,698
Granted
Jul 21, 2015
Kind
B2
Abstract

A thin-film transistor includes: a gate electrode above a substrate; a gate insulating layer above the gate electrode; a semiconductor layer opposed to the gate electrode with the gate insulating layer therebetween; a protective layer above the semiconductor layer and comprising an organic material; and a source electrode and a drain electrode each of which has at least a portion located above the protective layer. The protective layer includes an altered layer which has at least a portion contacting the semiconductor layer, and which is generated by alteration of a surface layer of the protective layer in a region exposed from the source electrode and the drain electrode. A relational expression of Log 10 Nt≦0.0556θ+16.86 is satisfied where Nt (cm −3 ) represents a defect density of the semiconductor layer and θ (°) represents a taper angle of an edge portion of the protective layer.

Claims (36)

1. A thin-film transistor comprising:

a gate electrode above a substrate;

a gate insulating layer above the gate electrode;

a semiconductor layer that is opposed to the gate electrode with the gate insulating layer therebetween;

an etch-stopper layer above the semiconductor layer and comprising an organic material; and

a source electrode and a drain electrode that are opposed to each other, each of the source electrode and the drain electrode having at least a portion located above the etch-stopper layer;

wherein the etch-stopper layer includes an altered layer having at least a portion contacting the semiconductor layer, the altered layer being generated by alteration of a surface layer of the etch-stopper layer in a region exposed from the source electrode and the drain electrode, and

a relational expression of Log 10 Nt≦0.0556θ+16.86 is satisfied where Nt (cm −3 ) represents a defect density of the semiconductor layer and θ (°) represents a taper angle of an edge portion of the region of the etch-stopper layer exposed from the source electrode and the drain electrode.

2. The thin-film transistor according to claim 1 ,

wherein the altered layer is a layer generated by dry etching performed to pattern the semiconductor layer.

3. The thin-film transistor according to claim 1 ,

wherein the altered layer has a thickness of at least 30 nm.

4. The thin-film transistor according to claim 2 ,

wherein the altered layer has a density higher than a density of a non-altered layer which is a portion of the etch-stopper layer that is not altered by the dry etching.

5. The thin-film transistor according to claim 4 ,

wherein the altered layer has a chlorine concentration which is at least ten times higher than a chlorine concentration of the non-altered layer.

6. The thin-film transistor according to claim 4 ,

wherein the altered layer has a carbon concentration which is at most one hundredth of a carbon concentration of the non-altered layer.

7. A method for manufacturing a thin-film transistor, the method comprising:

preparing a substrate;

forming a gate electrode above the substrate;

forming a gate insulating layer above the gate electrode;

forming a semiconductor film above the gate insulating layer;

forming, above the semiconductor film, an etch-stopper layer comprising an organic material;

forming a source electrode and a drain electrode that are opposed to each other, each of the source electrode and the drain electrode having at least a portion located above the etch-stopper layer; and

forming a semiconductor layer patterned, by performing dry etching on the semiconductor film;

wherein in the forming of a semiconductor layer, the dry etching (i) alters, into an altered layer, a surface layer of the etch-stopper layer in a region exposed from the source electrode and the drain electrode and (ii) etches the etch-stopper layer to have a taper angle at an edge portion of the exposed region, and

a relational expression of Log 10 Nt≦0.0556θ+16.86 is satisfied where Nt (cm −3 ) represents a defect density of the semiconductor layer and θ (°) represents the taper angle.

8. The method for manufacturing the thin-film transistor according to claim 7 ,

wherein the altered layer has a thickness of at least 30 nm.

9. The method for manufacturing the thin-film transistor according to claim 7 ,

wherein the altered layer has a density higher than a density of a portion of the etch-stopper layer that is not altered by the dry etching.

10. The method for manufacturing the thin-film transistor according to claim 9 ,

wherein the altered layer has a chlorine concentration which is at least ten times higher than a chlorine concentration of the non-altered layer.

11. The method for manufacturing the thin-film transistor according to claim 9 ,

wherein the altered layer has a carbon concentration which is at most one hundredth of a carbon concentration of the non-altered layer.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2025
From: JDI DESIGN AND DEVELOPMENT G.K.
To: MAGNOLIA BLUE CORPORATION
Reel/Frame 072039/0656 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2024
From: JOLED, INC.
To: JDI DESIGN AND DEVELOPMENT G.K.
Reel/Frame 066382/0619 →
CORRECTION BY AFFIDAVIT FILED AGAINST REEL/FRAME 063396/0671 Recorded Jun 12, 2023
From: JOLED, INC.
To: JOLED, INC.
Reel/Frame 064067/0723 →
SECURITY INTEREST Recorded Apr 20, 2023
From: JOLED, INC.
To: INCJ, LTD.
Reel/Frame 063396/0671 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 12, 2015
From: PANASONIC CORPORATION
To: JOLED INC
Reel/Frame 035187/0483 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 16, 2014
From: KISHIDA, YUJI; SATOH, EIICHI; KAWASHIMA, TAKAHIRO
To: PANASONIC CORPORATION
Reel/Frame 032908/0042 →