Data transmission circuit
View Patent ↗A data transmission circuit may include a first driving block configured to drive an output terminal for a first time in response to a data driving signal and a level of the output terminal, and a second driving block configured to drive the output terminal for a second time after the first time, in response to the data driving signal.
1. A data transmission circuit comprising:
a first driving block configured to drive an output terminal for a first time in response to a data driving signal and a level of the output terminal; and
a second driving block configured to drive the output terminal for a second time after the first time, in response to the data driving signal,
wherein the first driving block is configured to be controlled in its driving force in response to a test signal.
2. The data transmission circuit according to claim 1 , wherein the first driving block comprises logic elements which are designed to have different threshold voltages from logic elements of the second driving block.
3. The data transmission circuit according to claim 1 ,
wherein the first driving block and the second driving block comprise first type logic elements and second type logic elements, respectively, and
wherein the first type logic elements are designed to have relatively low threshold voltages when compared to the second type logic elements.
4. The data transmission circuit according to claim 1 , wherein the first driving block comprises:
a driver configured to drive the output terminal in response to the data driving signal; and
a driving control unit configured to open a current path of the driver for the first time in response to the level of the output terminal.
5. The data transmission circuit according to claim 1 , wherein the first driving block comprises:
a driver configured to drive the output terminal in response to the data driving signal; and
a driving control unit configured to control an amount of current to be supplied for the first time through a current path of the driver in response to the test signal.
6. The data transmission circuit according to claim 1 , wherein the first driving block comprises:
a driver configured to drive the output terminal in response to the data driving signal; and
a driving control unit configured to control a length of the first time in response to the test signal.
7. The data transmission circuit according to claim 6 , wherein the driving control unit comprises:
a transistor electrically coupled between a power supply terminal and the driver;
a plurality of delays configured to delay the level of the output terminal by different times and generate a plurality of control signals; and
a multiplexer configured to select one of the plurality of control signals in response to the test signal and apply the selected control signal to the transistor.
8. The data transmission circuit according to claim 1 , wherein the first driving block is activated during the first time, and the second driving block is activated during the second time after the first time if a data transits to a first level from a second level, and
wherein, in the first driving block and the second driving block, only the second driving block is activated if the data maintained the first level.
9. The data transmission circuit according to claim 8 , wherein the first level is logic high level and the second level is logic low level.
10. A data transmission circuit comprising:
a transmitter configured to drive an output terminal for a first time by using first type logic elements, interrupt the driving an output terminal for a first time which is proceeded by the first type logic elements, and drive the output terminal for a second time after the first time by using second type logic elements which are designed to have different threshold voltages from the first type logic elements; and
a receiver electrically coupled with the transmitter through a transmission line,
wherein the transmitter comprises:
a first driving block constituted by the first type logic elements, and configured to drive the output terminal for the first time in response to a data driving signal and a level of the output terminal; and
a second driving block constituted by the second type logic elements, and configured to drive the output terminal for the second time in response to the data driving signal, and
wherein the first driving block is configured to be controlled in its driving force in response to a test signal.
11. The data transmission circuit according to claim 10 , wherein the receiver is included in a controller outside a semiconductor apparatus including the transmitter, which instructs the semiconductor apparatus to input/output data.
12. The data transmission circuit according to claim 10 , wherein the receiver has an input terminal which is terminated to a level of a ground terminal through a termination resistor.
13. The data transmission circuit according to claim 10 , wherein the first driving block comprises:
a driver configured to drive the output terminal in response to the data driving signal; and
a driving control unit configured to open a current path of the driver for the first time in response to the level of the output terminal.
14. The data transmission circuit according to claim 10 , wherein the first driving block comprises:
a driver configured to drive the output terminal in response to the data driving signal; and
a driving control unit configured to control an amount of current to be supplied for the first time through a current path of the driver in response to the test signal.
15. The data transmission circuit according to claim 10 , wherein the first driving block comprises:
a driver configured to drive the output terminal in response to the data driving signal; and
a driving control unit configured to control a length of the first time in response to the test signal.