REFRESH SCHEME FOR MEMORY CELLS WITH WEAK RETENTION TIME
A memory refresh method within a memory controller includes checking a first retention state corresponding to a first memory address and a second retention state corresponding to a second memory address. The memory refresh method also includes performing a refresh operation on a row corresponding to the second memory address when the second retention state indicates a weak retention state. The first memory address corresponds to a refresh counter address, and the second memory address corresponds to a complementary address of the refresh counter address.
1 . A memory refresh method within a memory controller, comprising:
checking a first retention state corresponding to a first memory address and a second retention state corresponding to a second memory address; and
performing a refresh operation on a row corresponding to the second memory address when the second retention state indicates a weak retention state, in which the first memory address corresponds to a refresh counter address, and the second memory address corresponds to a complementary address of the refresh counter address.
2 . The memory refresh method of claim 1 , further comprising:
performing a refresh operation on a row corresponding to the first memory address after performing the refresh operation on the row corresponding to the second memory address; or
performing the refresh operation on the row corresponding to the first memory address before performing the refresh operation on the row corresponding to the second memory address.
3 . The memory refresh method of claim 1 , in which checking the first retention state comprises reading the first retention state of the first memory address and the second retention state of the second memory address from a one-time programmable memory.
4 . The memory refresh method of claim 3 , in which the one-time programmable memory includes each memory address and a retention state corresponding to each respective memory address.
5 . The memory refresh method of claim 3 , in which the one-time programmable memory includes each memory address having the weak retention state.
6 . The memory refresh method of claim 1 , in which checking the first retention state comprises determining whether a hit is detected with the first memory address or the second memory address from a weak row table.
7 . The memory refresh method of claim 1 , further comprising performing the refresh operation on a row corresponding to the first memory address concurrent with performing the refresh operation on the row corresponding to the second memory address.
8 . The memory refresh method of claim 1 , further comprising performing the refresh operation on a first plurality of internal rows corresponding to the first memory address concurrent with performing the refresh operation on an internal weak row from a second plurality of internal rows corresponding to the second memory address, the internal weak row being identified by the second retention state.
9 . The memory refresh method of claim 1 , in which the first memory address corresponds to the refresh counter address, and the second memory address corresponds to the refresh counter address with a complementary most significant bit.
10 . The memory refresh method of claim 1 , in which the memory refresh method is performed during a row address store (RAS) refresh cycle.
11 . The memory refresh method of claim 1 , in which the memory controller is integrated in a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit and/or a fixed location data unit.
12 . A memory controller, comprising:
a dynamic memory; and
a refresh control block coupled to the dynamic memory, the refresh control block including a refresh counter, a retention state table, and control logic, the control logic operable:
to check a first retention state corresponding to a first memory address from the retention state table and a second retention state corresponding to a second memory address from the retention state table, and
to insert a refresh operation when the second retention state indicates a weak retention state in which the first memory address corresponds to a refresh counter address, and the second memory address corresponds to a complementary address of the refresh counter address.
13 . The memory controller of claim 12 , in which the retention state table comprises a one-time programmable memory including each memory address and a retention state corresponding to each respective memory address.
14 . The memory controller of claim 12 , in which the retention state table comprises a one-time programmable memory including each memory address having the weak retention state.
15 . The memory controller of claim 12 , in which the control logic is further operable:
to perform a refresh operation on a row corresponding to the first memory address after the refresh operation on the row corresponding to the second memory address;
to perform the refresh operation on the row corresponding to the first memory address before the refresh operation on the row corresponding to the second memory address; or
to perform the refresh operation on a row corresponding to the first memory address concurrent the refresh operation on the row corresponding to the second memory address.
16 . The memory controller of claim 12 , in which the control logic is further operable to perform the refresh operation on a first plurality of internal rows corresponding to the first memory address concurrent with performing the refresh operation on an internal weak row from a second plurality of internal rows corresponding to the second memory address, the internal weak row being identified by the second retention state.
17 . The memory controller of claim 12 , in which the first memory address corresponds to the refresh counter address, and the second memory address corresponds to the refresh counter address with a complementary most significant bit.
18 . The memory controller of claim 12 , in which the memory controller is integrated in a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit and/or a fixed location data unit.
19 . A memory controller, comprising:
a dynamic memory; and
a refresh control block coupled to the dynamic memory, the refresh control block including a refresh counter, a retention state table, and control logic, the refresh control block comprising:
means for checking a first retention state corresponding to a first memory address from the refresh counter and a second retention state corresponding to a second memory address from the retention state table, and
means for performing a refresh operation on a row corresponding to the second memory address when the second retention state indicates a weak retention state.
20 . The memory controller of claim 19 , in which the memory controller further comprises:
means for performing a refresh operation on a row corresponding to the first memory address after performing the refresh operation on the row corresponding to the second memory address; or
means for performing the refresh operation on the row corresponding to the first memory address before performing the refresh operation on the row corresponding to the second memory address.
21 . The memory controller of claim 19 , in which the memory controller further comprises means for performing the refresh operation on a row corresponding to the first memory address concurrent with means for performing the refresh operation on the row corresponding to the second memory address.
22 . The memory controller of claim 19 , in which the memory controller further comprises means for performing the refresh operation on a first plurality of internal rows corresponding to the first memory address concurrent with means for performing the refresh operation on an internal weak row from a second plurality of internal rows corresponding to the second memory address, the internal weak row being identified by the second retention state.
23 . The memory controller of claim 19 , in which the retention state table comprises a one-time programmable memory including each memory address and a retention state corresponding to each respective memory address.
24 . The memory controller of claim 19 , in which the retention state table comprises a one-time programmable memory including each memory address having the weak retention state.
25 . The memory controller of claim 19 , in which the first memory address corresponds to a refresh counter address, and the second memory address corresponds to the refresh counter address with a complementary most significant bit.
26 . The memory controller of claim 19 , in which the memory controller is integrated in a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit and/or a fixed location data unit.
27 . A memory refresh method within a memory controller, comprising:
the step of testing a first retention state corresponding to a first memory address and a second retention state corresponding to a second memory address; and
the step of performing a refresh operation on a row corresponding to the second memory address when the second retention state indicates a weak retention state.
28 . The memory refresh method of claim 27 , in which the memory controller is integrated in a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit and/or a fixed location data unit.