Semiconductor device with logic circuit, SRAM circuit and standby state
View Patent ↗A semiconductor device is provided. The semiconductor device includes a logic circuit, an SRAM circuit coupled to a power line, and a switch coupled between the logic circuit and the power line. Before the switch is changed to an off position, a part of information held in the logic circuit is transferred to the SRAM circuit.
1. A semiconductor device comprising:
a first circuit block including a plurality of flip-flop circuits;
a second circuit block including a plurality of SRAM cells;
a first power line which supplies a first voltage to the first circuit block and the second circuit block; and
a first switch circuit coupled between the first circuit block and the first power line,
wherein the second circuit block is coupled to the first power line, and
wherein while a power supply of the first voltage to the plurality of flip-flop circuits is cut off by the first switch circuit, the plurality of SRAM cells are supplied with the first voltage from the first power line, and
wherein a part of information held in the plurality of flip-flop circuits is transferred to the plurality of SRAM cells before the first switch circuit is changed to an off status.
2. A semiconductor device according to claim 1 , further comprising:
a control circuit which controls substrate voltages of MIS transistors of the plurality of SRAM cells.
3. A semiconductor device according to claim 2 ,
wherein the control circuit is not coupled to the first circuit block.
4. A semiconductor device according to claim 2 ,
wherein, while the first switch circuit is in the off status, the control circuit controls the substrate voltages so as to reduce leakage current of the MIS transistors of the plurality of SRAM cells.
5. A semiconductor device according to claim 1 , further comprising:
a bus coupled between the first circuit block and the second circuit block,
wherein the part of information held in the plurality of flip-flop circuits is transferred to the plurality of SRAM cells.
6. A semiconductor device according to claim 1 ,
wherein a threshold voltage of each of MIS transistors of the plurality of flip-flop circuits is smaller than a threshold voltage of each of MIS transistors of the plurality of second cells.
7. A semiconductor device according to claim 6 ,
wherein a thickness of a gate insulating film of each of the MIS transistors of the plurality of flip-flop circuits is less than a thickness of a gate insulating film of each of the MIS transistors of the plurality of SRAM cells.
8. A semiconductor device according to claim 1
wherein a thickness of a gate insulating film of each of MIS transistors of the plurality of flip-flop circuits is less than a thickness of a gate insulating film of each of MIS transistors of the plurality of second SRAM cells.