IP Library Granted Patent US 9,526,185
Granted Patent B2
US 9,526,185 · App. 14/248,108 · Granted Dec 20, 2016

Hybrid PCB with multi-unreinforced laminate

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,526,185
App. No.
14/248,108
Granted
Dec 20, 2016
Kind
B2
Abstract

A hybrid printed circuit board may include a top layer, a bottom layer, and a plurality of internal layers stacked up between the top layer and the bottom layer. The plurality of internal layers may include a first internal layer below the top layer and a second internal layer above the bottom layer. The hybrid printed circuit board may include first unreinforced laminate placed between the top layer and the first internal layer. The hybrid circuit board may additionally include second unreinforced laminate placed between the second internal layer and the bottom layer. The hybrid printed circuit board may include third laminate placed between adjacent internal layers of the plurality of internal layers.

Claims (51)

1. A hybrid printed circuit board comprising:

a top layer;

a bottom layer;

a plurality of internal layers stacked up between the top layer and the bottom layer, the plurality of internal layers including a first internal layer below the top layer and a second internal layer above the bottom layer;

first unreinforced laminate placed between the top layer and the first internal layer;

second unreinforced laminate placed between the second internal layer and the bottom layer;

third laminate placed between adjacent internal layers of the plurality of internal layers; and

traces on at least one of a top side or a bottom side of the hybrid printed circuit board, wherein the traces each have a width less than 75 micrometers.

2. The hybrid printed circuit board of claim 1 , wherein the first unreinforced laminate and the second unreinforced laminate include glass-free dielectric material.

3. The hybrid printed circuit board of claim 1 , wherein the first unreinforced laminate and the second unreinforced laminate include one of glass-free polyimide, liquid crystal polymer, and ZetaLam.

4. The hybrid printed circuit board of claim 1 , wherein the third laminate includes reinforced laminate.

5. The hybrid printed circuit board of claim 4 , wherein the reinforced laminate includes glass-reinforced epoxy laminate.

6. The hybrid printed circuit board of claim 5 , wherein the glass-reinforced epoxy laminate includes flame retardant 4 (FR-4).

7. The hybrid printed circuit board of claim 4 , wherein the reinforced laminate includes Megtron VI.

8. The hybrid printed circuit board of claim 4 , wherein the reinforced laminate includes pre-impregnated (PREPREG) composite fibers.

9. The hybrid printed circuit board of claim 1 , wherein a surface finish of the hybrid printed circuit board includes palladium.

10. A hybrid printed circuit board comprising:

a top layer;

a bottom layer;

a plurality of internal layers stacked up between the top layer and the bottom layer, the plurality of internal layers including a first internal layer below the top layer and a second internal layer above the bottom layer;

first unreinforced laminate placed between the top layer and the first internal layer;

second unreinforced laminate placed between the second internal layer and the bottom layer; and

third laminate placed between adjacent internal layers of the plurality of internal layers;

wherein a surface finish of the hybrid printed circuit board includes palladium and a thickness of the palladium is about 0.5 micrometer.

11. The hybrid printed circuit board of claim 9 , wherein the surface finish comprises electroless nickel electroless palladium immersion gold (ENEPIG) surface finish.

12. A hybrid printed circuit board comprising:

a top copper-foil layer;

a bottom copper-foil layer;

a plurality of internal copper-foil layers stacked up between the top copper-foil layer and the bottom copper-foil layer, the plurality of internal copper-foil layers including a first internal copper-foil layer below the top copper-foil layer and a second internal copper-foil layer above the bottom copper-foil layer;

first unreinforced laminate between the top copper-foil layer and the first internal copper-foil layer;

second unreinforced laminate between the second internal copper-foil layer and the bottom copper-foil layer; and

third laminate placed between adjacent internal copper-foil layers of the plurality of internal copper-foil layers.

13. The hybrid printed circuit board of claim 1 , wherein the width of each of the traces is 50 micrometers and a trace pitch of the traces is 110 micrometers.

14. The hybrid printed circuit board of claim 1 , wherein the width of each of the traces is between 50 micrometers and 60 micrometers and a trace pitch of the traces is between 100 micrometers and 110 micrometers.

15. The hybrid printed circuit board of claim 1 , wherein the hybrid printed circuit board is configured to operate at a transmission speed of at least about 25 gigabits per second per channel.

16. A hybrid printed circuit board comprising:

a top layer;

a bottom layer;

a plurality of internal layers stacked up between the top layer and the bottom layer, the plurality of internal layers including a first internal layer below the top layer and a second internal layer above the bottom layer;

first unreinforced laminate placed between the top layer and the first internal layer;

second unreinforced laminate placed between the second internal layer and the bottom layer; and

third laminate placed between adjacent internal layers of the plurality of internal layers;

wherein the hybrid printed circuit board has a thickness of 1 millimeter with a deviation between −10% to +10%.

17. The hybrid printed circuit board of claim 1 , wherein the hybrid printed circuit board has a total number of four copper-foil layers including the top layer, the first internal layer, the second internal layer, and the bottom layer.

18. The hybrid printed circuit board of claim 1 , wherein:

the hybrid printed circuit board has a total number of eight layers including the top layer, the bottom layer, and six internal layers stacked up between the top layer and the bottom layer; and

the six internal layers include the first internal layer, the second internal layer, and four additional internal layers stacked up between the first internal layer and the second internal layer.

19. The hybrid printed circuit board of claim 1 , wherein:

the hybrid printed circuit board has a total number of ten layers including the top layer, the bottom layer, and eight internal layers stacked up between the top layer and the bottom layer; and

the eight internal layers includes the first internal layer, the second internal layer, and six additional internal layers stacked up between the first internal layer and the second internal layer.

20. The hybrid printed circuit board of claim 1 , wherein a thickness of each of the first unreinforced laminate and the second unreinforced laminate is about 37 micrometers.

Assignments (5)
PATENT RELEASE AND REASSIGNMENT Recorded Jul 5, 2022
From: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
To: II-VI INCORPORATED; MARLOW INDUSTRIES, INC.; EPIWORKS, INC.; LIGHTSMYTH TECHNOLOGIES, INC.; KAILIGHT PHOTONICS, INC.; COADNA PHOTONICS, INC.; OPTIUM CORPORATION; FINISAR CORPORATION; II-VI OPTICAL SYSTEMS, INC.; M CUBED TECHNOLOGIES, INC.; II-VI PHOTONICS (US), INC.; II-VI DELAWARE, INC.; II-VI OPTOELECTRONIC DEVICES, INC.; PHOTOP TECHNOLOGIES, INC.
Reel/Frame 060574/0001 →
SECURITY INTEREST Recorded Jul 1, 2022
From: II-VI INCORPORATED; II-VI DELAWARE, INC.; M CUBED TECHNOLOGIES, INC.; II-VI PHOTONICS (US), INC.; PHOTOP TECHNOLOGIES, INC.; COHERENT, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 060562/0254 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 1, 2020
From: FINISAR CORPORATION
To: II-VI DELAWARE, INC.
Reel/Frame 052286/0001 →
NOTICE OF GRANT OF SECURITY INTEREST IN PATENTS Recorded Sep 25, 2019
From: II-VI INCORPORATED; MARLOW INDUSTRIES, INC.; EPIWORKS, INC.; LIGHTSMYTH TECHNOLOGIES, INC.; KAILIGHT PHOTONICS, INC.; COADNA PHOTONICS, INC.; OPTIUM CORPORATION; FINISAR CORPORATION; II-VI OPTICAL SYSTEMS, INC.; M CUBED TECHNOLOGIES, INC.; II-VI PHOTONICS (US), INC.; II-VI DELAWARE, INC.; II-VI OPTOELECTRONIC DEVICES, INC.; PHOTOP TECHNOLOGIES, INC.
To: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 050484/0204 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 8, 2014
From: DAGHIGHIAN, HENRY MEYER; BIRD, STEVEN C.; BABEL, GERALD DOUGLAS
To: FINISAR CORPORATION
Reel/Frame 032630/0198 →