Display substrate including a thin film transistor and method of manufacturing the same
A method of manufacturing a display substrate includes forming a gate electrode on a base substrate, forming an active pattern which includes an oxide semiconductor and overlaps with the gate electrode, forming an etch stopper which partially covers the active pattern, and performing a plasma treatment process to promote a reduction reaction to portions of the active pattern exposed by the etch stopper, thereby forming a source electrode and a drain electrode.
1. A method of manufacturing a display substrate, the method comprising:
forming a gate electrode on a base substrate;
forming an oxide semiconductor layer on the gate electrode;
forming an insulation layer on the oxide semiconductor layer;
forming a first photoresist pattern on the insulation layer;
partially removing the insulation layer and the oxide semiconductor layer using the first photoresist pattern as an etching mask to form an active pattern;
forming a protective pattern which partially covers the active pattern, from the insulation layer; and
performing a plasma treatment process to promote a reduction reaction to portions of the active pattern exposed by the protective pattern, thereby forming a source electrode and a drain electrode.
2. The method of claim 1 , wherein the source electrode and the drain electrode are exposed by the protective pattern.
3. The method of claim 1 , wherein the plasma treatment process is performed in an atmosphere including a hydrogen gas.
4. The method of claim 3 , wherein the forming the source electrode and the drain electrode comprises reducing indium from the oxide semiconductor of the active pattern.
5. The method of claim 1 , wherein the plasma treatment process is performed in an atmosphere including a fluorine gas.
6. The method of claim 5 , wherein the forming the source electrode and the drain electrode comprises implanting fluorine at upper portions of the active pattern.
7. The method of claim 1 , wherein the first photoresist pattern includes a first thickness portion and a second thickness portion, and wherein the second thickness portion is thinner than the first thickness portion.
8. The method of claim 7 , wherein the forming the first photoresist pattern comprises using a slit mask.
9. The method of claim 7 , wherein the forming the first photoresist pattern comprises using a half-tone mask.
10. The method of claim 1 , wherein the forming the protective pattern comprises:
exposing the first photoresist pattern from a back side of the base substrate using the gate electrode as an exposure mask;
partially removing the first photoresist pattern to provide a remaining photoresist pattern; and
partially removing the insulation layer using the remaining photoresist pattern as the etching mask.
11. The method of claim 1 , wherein the forming the oxide semiconductor layer comprises:
forming a first oxide semiconductor layer including a first oxide semiconductor, the first oxide semiconductor layer overlapping with the gate electrode; and
forming a second oxide semiconductor layer including a second oxide semiconductor on the first oxide semiconductor layer.
12. The method of claim 11 , wherein the second oxide semiconductor includes an indium content higher than that of the first oxide semiconductor.
13. The method of claim 12 , wherein the forming the source electrode and the drain electrode comprises performing the plasma treatment process to promote the reduction reaction to portions of the second active pattern.