Stacked semiconductor structure and method

1. A method comprising:

providing a first chip comprising a plurality of first active circuits and a first connection pad formed of a first conductive material;

depositing a first dielectric layer over the first chip;

forming a first bonding pad on the first connection pad, wherein:

the first bonding pad is in direct contact with the first connection pad; and

the first bonding pad is formed of a second conductive material;

providing a second chip comprising a plurality of second active circuits;

depositing a second dielectric layer over the second chip;

forming a second bonding pad in the second dielectric layer, wherein the second bonding pad is formed of the second conductive material;

stacking the first chip on the second chip, wherein the first bonding pad is in direct contact with the second bonding pad; and

bonding the first chip and the second chip together, wherein:

the first bonding pad is electrically coupled to the second bonding pad; and

the first active circuits are electrically coupled to the second active circuits.

2. The method of claim 1 , further comprising:

bonding the first chip and the second chip through a hybrid bonding process.

3. The method of claim 1 , wherein:

the first conductive material is aluminum; and

the second conductive material is copper.

4. The method of claim 1 , further comprising:

after the step of bonding the first chip and the second chip, thinning a backside of the second chip.

5. The method of claim 4 , further comprising:

after the step of thinning the backside of the second chip, forming a second connection pad on the backside of the second chip.

6. The method of claim 1 , further comprising:

applying an annealing process to the first chip and the second chip after the step of stacking the first chip on the second chip.

7. The method of claim 6 , further comprising:

forming a uniform bonded feature through an inter-diffusion process between the first bonding pad and the second bonding pad.

8. A method comprising:

providing a first chip comprising a plurality of first active circuits and a first aluminum connection pad, wherein the first active circuits are formed adjacent to a first side of the first chip;

depositing a first dielectric layer on the first side of the first chip;

forming a first copper bonding pad on the first aluminum connection pad;

providing a second chip comprising a plurality of second active circuits, wherein the second active circuits are formed adjacent to a first side of the second chip;

depositing a second dielectric layer on the first side of the second chip;

forming a second copper bonding pad in the second dielectric layer;

stacking the first chip on the second chip, wherein the first copper bonding pad is in direct contact with the second copper bonding pad; and

bonding the first chip and the second chip to form a uniform bonded feature.

9. The method of claim 8 , further comprising:

bonding the first chip and the second chip, wherein:

the first copper bonding pad is electrically coupled to the second copper bonding pad; and

the first active circuits are electrically coupled to the second active circuits.

10. The method of claim 8 , wherein:

the first side of the first chip is face-to-face bonded on the first side of the second chip.

11. The method of claim 8 , further comprising:

applying a planarization process to thin a second side of the second chip.

12. The method of claim 11 , further comprising:

after the step of applying the planarization process to thin the second side of the second chip, forming a second aluminum connection pad on the second side of the second chip.

13. The method of claim 12 , wherein:

the second aluminum connection pad is electrically coupled to the first active circuits through the uniform bonded feature.

14. A method comprising:

depositing a first dielectric layer over a first chip comprising a plurality of first active circuits and a first connection pad, wherein a top surface of the first connection pad is lower than a top surface of the first dielectric layer and the plurality of first active circuits are adjacent to a first side of the first chip;

forming a connector over the first connection pad, wherein a bottom surface of the connector is in direct contact with the top surface of the first connection pad and a top surface of the connector is level with the top surface of the first dielectric layer;

forming a first bonding pad over the first chip, wherein the first bonding pad is in direct contact with the connector and a width of the first bonding pad is greater than a width of the connector;

depositing a second dielectric layer over a second chip comprising a plurality of second active circuits adjacent to a first side of the second chip;

forming a second bonding pad in the second dielectric layer, wherein a width of the second bonding pad is greater than a width of the first bonding pad; and

stacking the first side of the first chip on the first side of the second chip, wherein the first bonding pad is in direct contact with the second bonding pad.

15. The method of claim 14 , further comprising:

bonding the first chip and the second chip together through a hybrid bonding process, wherein:

the first bonding pad is electrically coupled to the second bonding pad; and

the first active circuits are electrically coupled to the second active circuits.

16. The method of claim 14 , further comprising:

forming a third bonding pad over the first chip, wherein a distance between the third bonding pad and the first bonding pad is at least four times greater than the width of the first bonding pad; and

forming a fourth bonding pad over the second chip, wherein a distance between the fourth bonding pad and the second bonding pad is at least four times greater than the width of the second bonding pad.

17. The method of claim 16 , wherein:

the third bonding pad is in direct contact with the fourth bonding pad.

18. The method of claim 16 , wherein:

the fourth bonding pad and the second bonding pad are in direct contact with a same metal line of the second chip.

19. The method of claim 14 , wherein:

the first connection pad is formed of aluminum;

the connector is formed of tungsten; and

the first bonding pad is formed of copper.

20. The method of claim 14 , further comprising:

thinning a second side of the second chip;

removing a portion of the second chip; and

forming connection pads on the second side of the second chip.