Testing fuse configurations in semiconductor devices
View Patent ↗A system includes a first integrated circuit configured to operate in at least a normal mode and a test mode and a second integrated circuit, where both the first integrated circuit and the second integrated circuit are disposed within a same semiconductor device package. The system further includes a first terminal, external to the semiconductor device package, electronically coupled to the first integrated circuit and the second integrated circuit. The first terminal is electronically coupled to a buffer in the second integrated circuit and used to convey signals to or from the first integrated circuit.
1. A system comprising:
a first integrated circuit configured to operate in at least a normal mode and a test mode, wherein the first integrated circuit comprises a memory device, the memory device comprising a latch and a fuse, the latch to receive fuse configuration data and to output a soft-blow signal based on the fuse configuration data, the soft-blow signal to configure the fuse;
a second integrated circuit comprising a buffer, wherein the second integrated circuit comprises a memory controller, both the first integrated circuit and the second integrated circuit being disposed within the same semiconductor device package;
a first terminal external to the semiconductor device package, electronically coupled to the first integrated circuit and the second integrated circuit, the first terminal electronically coupled to the buffer in the second integrated circuit and used to convey signals to or from the first integrated circuit.
2. The system of claim 1 , wherein the buffer comprises a normal mode buffer.
3. The system of claim 2 , wherein the first terminal is configured to convey the signals between the normal mode buffer and the first integrated circuit when the first integrated circuit is in the normal mode.
4. The system of claim 1 , wherein the buffer comprises a test mode buffer.
5. The system of claim 4 , wherein the first terminal is configured to convey the signals between the test mode buffer and the first integrated circuit when the first integrated circuit is in the test mode.
6. The system of claim 1 , wherein the buffer comprises at least one of a normal mode buffer or a test mode buffer, the system further comprising:
an input to receive a signal to activate one of the normal mode buffer or the test mode buffer, wherein only one of the normal mode buffer and the test mode buffer is activated at the same time.
7. A method comprising:
receiving a signal at a first terminal external to a semiconductor package, the semiconductor package comprising a first integrated circuit configured to operate in at least a normal mode and a test mode and a second integrated circuit comprising a buffer, wherein the first integrated circuit comprises a memory device and wherein the second integrated circuit comprises a memory controller, the memory device comprising a latch and a fuse, the latch to receive fuse configuration data and to output a soft-blow signal based on the fuse configuration data, the soft-blow signal to configure the fuse; and
conveying the signal from the first terminal to or from the first integrated circuit, wherein the first terminal is electronically coupled to the buffer in the second integrated circuit.
8. The method of claim 7 , wherein the buffer comprises a normal mode buffer.
9. The method of claim 8 , wherein the first terminal is configured to convey the signals between the normal mode buffer and the first integrated circuit when the first integrated circuit is in the normal mode.
10. The method of claim 7 , wherein the buffer comprises a test mode buffer.
11. The method of claim 10 , wherein the first terminal is configured to convey the signals between the test mode buffer and the first integrated circuit when the first integrated circuit is in the test mode.
12. The method of claim 7 , wherein the buffer comprises at least one of a normal mode buffer or a test mode buffer, the method further comprising:
receiving a signal at an input, the signal to activate one of the normal mode buffer or the test mode buffer, wherein only one of the normal mode buffer and the test mode buffer is activated at the same time.
13. A system comprising:
a logic device configured to operate in at least a normal mode and a test mode, wherein the logic device comprises a memory device, the memory device comprising a latch array and a fuse array, the latch array to receive fuse configuration data and to output a soft-blow signal based on the fuse configuration data, the soft-blow signal to configure the fuse array;
an integrated circuit comprising a buffer, wherein the integrated circuit comprises a memory controller, both the logic device and the integrated circuit being disposed within the same semiconductor device package; and
a first terminal external to the semiconductor device package, electronically coupled to the logic device and the integrated circuit, and configured to operate as a shared input for the logic device and the integrated circuit, the first terminal electronically coupled to the buffer in the integrated circuit and used to convey signals to or from the logic device.
14. The system of claim 13 , wherein the buffer comprises one of a normal mode buffer or a test mode buffer.
15. The system of claim 14 , wherein the first terminal is configured to convey the signals between the normal mode buffer and the logic device when the logic device is in the normal mode.
16. A The system of claim 14 , wherein the first terminal is configured to convey the signals between the test mode buffer and the logic device when the logic device is in the test mode.
17. The system of claim 14 , further comprising:
an input to receive a signal to activate one of the normal mode buffer and the test mode buffer, wherein only one of the normal mode buffer and the test mode buffer is activated at the same time.