IP Library Granted Patent US 9,384,088
Granted Patent B1
US 9,384,088 · App. 14/250,212 · Granted Jul 5, 2016

Double writing map table entries in a data storage system to guard against silent corruption

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Quick Facts
Patent No.
US 9,384,088
App. No.
14/250,212
Granted
Jul 5, 2016
Kind
B1
Abstract

A method for writing data in a data storage device includes: writing data to a physical memory location in a non-volatile memory; writing, for a first time, to a location in a volatile memory corresponding to a logical address of the data, a physical address of the physical memory location of the non-volatile memory containing the data; and writing, for a second time, to the location in the volatile memory corresponding to the logical address of the data, the address of the physical memory location of the non-volatile memory containing the data. The physical address of the physical memory location is written with appended error detection code information, and the error detection code information is determined based on the logical address of the data.

Claims (28)

1. A method for writing data in a data storage device using a control unit, the method comprising:

writing, by the control unit, data to a physical memory location in a non-volatile memory;

sending, by the control unit, a first update request corresponding to the data to write a physical address of the physical memory location to a location in a volatile memory corresponding to a logical address of the data; and

sending, by the control unit, a second update request corresponding to the data to write the physical address of the physical memory location to the location in the volatile memory corresponding to the logical address of the data, thereby reducing a probability of writing the physical address of the physical memory location to a wrong location in the volatile memory;

wherein the physical address of the physical memory location is written with appended error detection code information, and

the error detection code information is determined based on the logical address of the data.

2. The method of claim 1 , wherein the location in the volatile memory comprises at least a portion of a map table.

3. The method of claim 2 , wherein the map table is arranged with memory locations assigned according to a consecutive order.

4. The method of claim 1 , wherein the data is received from a host.

5. The method of claim 1 , wherein the data is read from another physical address of the non-volatile memory prior to writing the data to the physical memory location.

6. The method of claim 5 , further comprising modifying the data read from the other physical address of the non-volatile memory before writing the data.

7. A data storage device, comprising:

a non-volatile memory;

a volatile memory;

a control unit configured to:

write data to a physical memory location in the non-volatile memory;

send a first update request corresponding to the data to write a physical address of the physical memory location to a location in a volatile memory corresponding to a logical address of the data; and

send a second update request corresponding to the data to write the physical address of the physical memory location to the location in the volatile memory corresponding to the logical address of the data, thereby reducing a probability of writing the physical address of the physical memory location to a wrong location in the volatile memory,

wherein the address of the physical memory location is written with appended error detection code information, and

the error detection code information is determined based on the logical address of the data.

8. The data storage device of claim 7 , wherein the volatile memory comprises a map table.

9. The data storage device of claim 8 , wherein the map table is arranged with memory locations assigned according to a consecutive order.

10. The data storage device of claim 7 , wherein the volatile memory is dynamic random access memory (DRAM).

11. The data storage device of claim 7 , wherein the non-volatile memory is a non-volatile semiconductor memory (NVSM).

12. The data storage device of claim 11 , wherein the NVSM comprises NAND flash memory devices.

13. The data storage device of claim 7 , wherein the data is received from a host.

14. The data storage device of claim 7 , wherein the data is read from another physical address of the non-volatile memory prior to writing the data to the physical memory location.

15. The data storage device of claim 14 , wherein the control unit is further configured to modify the data read from the other physical address of the non-volatile memory before writing the data.

Assignments (14)
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 038744 FRAME 0481 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058982/0556 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2018
From: SKYERA, LLC
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 046726/0328 →
RELEASE OF SECURITY INTEREST Recorded Mar 5, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 045501/0714 →
SECURITY AGREEMENT Recorded May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 038744/0481 →
SECURITY AGREEMENT Recorded May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 038722/0229 →
SECURITY AGREEMENT Recorded May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038744/0281 →
CHANGE OF NAME Recorded Jul 17, 2015
From: SKYERA, INC.
To: SKYERA, LLC
Reel/Frame 036129/0673 →
RELEASE OF SECURITY INTEREST Recorded Jan 6, 2015
From: DELL PRODUCTS L.P.
To: SKYERA, LLC
Reel/Frame 034742/0069 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 6, 2015
From: MULLENDORE, RODNEY N.
To: SKYERA, INC.
Reel/Frame 034648/0286 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 6, 2015
From: JONES, JUSTIN; TOMLIN, ANDREW J.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 034648/0273 →
SECURITY INTEREST Recorded Nov 11, 2014
From: SKYERA, INC.
To: WESTERN DIGITAL CAPITAL, INC.
Reel/Frame 034204/0849 →
SECURITY INTEREST Recorded Aug 14, 2014
From: SKYERA, INC.
To: DELL PRODUCTS L.P.
Reel/Frame 033546/0001 →