3D non-volatile memory device and method for fabricating the same
View Patent ↗A non-volatile memory device having a string of a plurality of memory cells that are serially coupled, wherein the string of memory cells includes a plurality of second channels of a pillar type, a first channel coupling lower end portions of the plurality of the second channels with each other, and a plurality of control gate electrodes surrounding the plurality of the second channels.
1. A method of fabricating a non-volatile memory device having a pillar type channel, comprising:
forming a first trench by etching a substrate;
forming a first channel by filling a first channel material in the first trench;
stacking a plurality of first material layers and a plurality of second material layers over the substrate filled with the first channel;
forming a plurality of second trenches by etching the plurality of the first material layers and the plurality of the second material layer that expose the first channel; and
forming a plurality of second channels by filling a second channel material in the plurality of the second trenches and coupled lower end portions of the plurality of the second channels with each other,
wherein the forming of the first trench comprises:
forming a first sub-trench by etching the substrate; and
forming a second sub-trench having a narrower width than a width of the first sub-trench by etching a bottom surface of the first sub-trench.
2. The method of claim 1 , further comprising:
filling the second sub-trench with gate electrode material to form a back gate electrode, after the forming of the first trench; and
forming a gate insulation layer over the substrate filled with the back gate electrode.
3. The method of claim 1 , further comprising:
forming a protective layer over the substrate including the first channel, after the forming the first channel.
4. The method of claim 3 , wherein the forming of the protective layer further comprises:
stacking a first etch stop layer, a buffer layer, and a second etch stop layer.
5. The method of claim 4 , wherein the first and second etch stop layers are nitride layers, and the buffer layer is an oxide layer.
6. The method of claim 1 , further comprising:
forming a third trench by etching the first material layers and the second material layers at an area between the second channels after the forming of the plurality of the second channels; and
filling the third trench with an isolation layer.
7. The method of claim 1 , wherein the first material layers are oxide layers, and the second material layers are polysilicon layers, the polysilicon layers forming control gate electrodes.
8. The method of claim 7 , further comprising:
forming a charge blocking layer, a charge storage or charge trapping layer, and a tunnel insulation layer on internal sidewalls of the plurality of the second trenches before the forming the plurality of the second channels.
9. The method of claim 1 , wherein the first material layers are oxide layers, and the second material layers are sacrificial layers.
10. The method of claim 9 , wherein the sacrificial layers having etch selectivity of the first material layers.
11. The method of claim 9 , further comprising:
forming an undercut which exposes a external sidewalls of each second channel between the first material layers by removing the second material layers after the forming of the plurality of the second channels;
forming a tunnel insulation layer, a charge storage or charge trapping layer, and a charge blocking layer surrounding the first material layer and the exposed sidewall of the second channel; and
forming a control gate electrode by filling the undercut over the charge blocking layer, the charge storage or charge trapping layer, and the tunnel insulation layer.
12. The method of claim 1 , further comprising:
forming a plurality of select transistors including third channels extended from upper end portions of the plurality of the second channels and select gate electrodes surrounding the third channels after the forming of the plurality of the second channels.
13. The method of claim 12 , further comprising:
forming a source line coupled with an upper end portion of a portion of the third channels after forming the plurality of the select transistors; and
forming a bit line coupled with an upper end portion of a remaining portion of the third channels.
14. A method of fabricating a non-volatile memory device having a pillar type channel, comprising:
forming a first trench by etching a substrate;
forming a first channel by filling a first channel material in the first trench;
stacking a plurality of first material layers and a plurality of second material layers over the substrate filled with the first channel;
forming a plurality of second trenches by etching the plurality of the first material layers and the plurality of the second material layer that expose the first channel; and
forming a plurality of second channels by filling a second channel material in the plurality of the second trenches and coupled lower end portions of the plurality of the second channels with each other,
wherein the forming of the first trench comprises:
forming a second sub-trench by etching the substrate; and
forming a first sub-trench having a wider width than a width of the second sub-trench by increasing the width of an upper portion of the second sub-trench through an isotropic etch process.
15. The method of claim 14 , further comprising:
filling the second sub-trench with gate electrode material to form a back gate electrode, after the forming of the first trench; and
forming a gate insulation layer over the substrate filled with the back gate electrode.