Double patterning layout design method

1. A double patterning layout design method, comprising:

defining critical paths comprising a first path and a second path on a schematic circuit; and

defining a double patterning layout divided into a first mask layout having a first color and a second mask layout having a second color, the double patterning layout corresponding to the schematic circuit,

wherein the defining the critical paths and the defining of the double patterning layout are performed using a processor,

wherein the defining of the double patterning layout comprises anchoring the critical paths on the schematic circuit by pre-defining colored layouts of polygons corresponding to the critical paths, and

wherein the pre-defining of the colored layouts of the polygons corresponding to the critical paths comprises applying a plurality of colors to a first polygon corresponding to the first path, applying the plurality of colors to a second polygon corresponding to the second path, and matching color ratios of the first polygon and the second polygon.

2. The double patterning layout design method of claim 1 , wherein the defining of the critical paths comprises defining a first signal line and a second signal line which are critical to timing on the schematic circuit as the first path and the second path, respectively.

3. A double patterning layout design method comprising:

defining critical paths comprising a first path and a second path on a schematic circuit; and

defining a double patterning layout divided into a first mask layout having a first color and a second mask layout having a second color, the double patterning layout corresponding to the schematic circuit,

wherein the defining the critical paths and the defining of the double patterning layout are performed using a processor,

wherein the defining of the double patterning layout further comprises defining a colorless layout corresponding to the schematic circuit, wherein the anchoring of the critical paths on the schematic circuit comprises anchoring the critical paths by pre-coloring polygons corresponding to the critical paths on the colorless layout, and

wherein the pre-coloring of the polygons corresponding to the critical paths comprises applying a plurality of colors to a first polygon corresponding to the first path, applying the plurality of colors to a second polygon corresponding to the second path, and matching color ratios of the first polygon and the second polygon.

4. A double patterning layout design method comprising:

receiving information on a defined schematic circuit and critical paths defined on the schematic circuit;

defining a double patterning layout divided into a first mask layout having a first color and a second mask layout having a second color, the double patterning layout corresponding to the schematic circuit; and

outputting the defined double patterning layout,

wherein the defining of the double patterning layout is performed using a processor,

wherein the defining of the double patterning layout comprises anchoring the critical paths on the schematic circuit by pre-defining colored layouts of polygons corresponding to the critical paths, and

wherein the pre-defining of the colored layouts of the polygons corresponding to the critical paths comprises applying a plurality of colors to a first polygon corresponding to the first path, applying the plurality of colors to a second polygon corresponding to the second path, and matching color ratios of the first polygon and the second polygon.

5. A double patterning layout design method comprising:

receiving information on a defined schematic circuit and critical paths defined on the schematic circuit;

defining a double patterning layout divided into a first mask layout having a first color and a second mask layout having a second color, the double patterning layout corresponding to the schematic circuit; and

outputting the defined double patterning layout,

wherein the defining of the double patterning layout is performed using a processor,

wherein the defining of the double patterning layout further comprises defining a colorless layout corresponding to the schematic circuit, wherein the anchoring of the critical paths on the schematic circuit comprises anchoring the critical paths by pre-coloring polygons corresponding to the critical paths on the colorless layout, and

wherein the pre-coloring of the polygons corresponding to the critical paths comprises applying a plurality of colors to a first polygon corresponding to the first path, applying the plurality of colors to a second polygon corresponding to the second path, and matching color ratios of the first polygon and the second polygon.

6. A system configured to design a double patterning layout, comprising:

a processor configured to define critical paths comprising a first path and a second path on a schematic circuit and define a double patterning layout divided into a first mask layout having a first color and a second mask layout having a second color, the double patterning layout corresponding to the schematic circuit,

wherein the defining of the double patterning layout comprises anchoring the critical paths on the schematic circuit by pre-defining colored layouts of polygons corresponding to the critical paths, and

wherein the pre-defining of the colored layouts of the polygons corresponding to the critical paths comprises applying a plurality of colors to a first polygon corresponding to the first path, applying the plurality of colors to a second polygon corresponding to the second path, and matching color ratios of the first polygon and the second polygon.

7. The system of claim 6 , wherein the defining of the critical paths comprises defining a first signal line and a second signal line which are critical to timing on the schematic circuit as the first path and the second path, respectively.