IP Library Granted Patent US 10,854,764
Granted Patent B2
US 10,854,764 · App. 14/258,638 · Granted Dec 1, 2020

Solar cell and method for manufacturing the same

Inventors: Minho Choi (Seoul, KR); Hyunjung Park (Seoul, KR); Junghoon Choi (Seoul, KR)
Assignee: LG ELECTRONICS INC.
H01L31/02167H01L31/022441H01L31/072H01L31/0745H01L31/0747H01L31/1804Y02E10/547Y02P70/521
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Quick Facts
Patent No.
US 10,854,764
App. No.
14/258,638
Granted
Dec 1, 2020
Kind
B2
Abstract

A solar cell includes a semiconductor substrate, a tunneling layer on one surface of the semiconductor substrate, a first conductive type area on the tunneling layer, a second conductive type area on the tunneling layer such that the second conductive type area is separated from the first conductive type area, and a barrier area interposed between the first conductive type area and the second conductive type area such that the barrier area separates the first conductive type area from the second conductive type area.

Claims (20)

1. A method for manufacturing a solar cell comprising:

forming a tunneling layer entirely on a first surface of a semiconductor substrate;

forming a first conductive type area and a second conductive type area on the tunneling layer,

wherein the first conductive type area and the second type area are deposited directly on the tunneling layer;

separately forming a barrier area to separate the first conductive type area and the second conductive type area;

forming a front surface field layer having a conductive type the same as the base area and having a high doping concentration higher than the base area on a second surface of the semiconductor substrate;

forming a passivation layer formed on the first and second conductive type areas and the barrier area;

forming a first electrode connected to the first conductive type area by penetrating a first contact hole of the passivation layer and a second electrode connected to the second conductive type area by penetrating a second contact hole of the passivation layer,

wherein the first conductive type area comprises amorphous silicon, microcrystalline silicon, or polycrystalline silicon including the first conductive type dopant,

wherein the second conductive type area comprises amorphous silicon, microcrystalline silicon, or polycrystalline silicon including the second conductive type dopant;

wherein the barrier area comprises amorphous silicon, microcrystalline silicon, or polycrystalline silicon being intrinsic,

wherein the first conductivity type area and the second conductivity type area have a continuously uniform thickness, and the barrier layer also has a continuously uniform thickness, and

the barrier area has the thickness greater than the thickness of the first and second conductive areas.

2. The method according to claim 1 , wherein the doping comprises:

forming a first doping layer including the first conductive type dopant on the semiconductor layer;

forming an undoped layer on the first doping layer and on a portion of the semiconductor layer adjacent to the first doping layer;

forming a second doping layer including the second conductive type dopant over the entire undoped layer and the semiconductor layer; and

diffusing the first conductive type dopant and the second conductive type dopant into the semiconductor layer to simultaneously form a first conductive type area and a second conductive type area,

wherein, after the diffusing, a portion of the semiconductor layer into which the first conductive type dopant is diffused constitutes the first conductive type area, and a portion of the semiconductor layer into which the second conductive type dopant is diffused constitutes the second conductive type area.

3. The method according to claim 2 , wherein one of the first doping layer and the second doping layer comprises boron silicate glass (BSG) and the other of the first doping layer and the second doping layer comprises phosphorous silicate glass (PSG).

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 18, 2024
From: SHANGRAO XINYUAN YUEDONG TECHNOLOGY DEVELOPMENT CO., LTD.
To: TRINA SOLAR CO., LTD.
Reel/Frame 066802/0483 →
CHANGE OF NAME Recorded Nov 30, 2023
From: SHANGRAO JINKO SOLAR TECHNOLOGY DEVELOPMENT CO., LTD
To: SHANGRAO XINYUAN YUEDONG TECHNOLOGY DEVELOPMENT CO. LTD
Reel/Frame 065725/0706 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 29, 2022
From: LG ELECTRONICS INC.
To: SHANGRAO JINKO SOLAR TECHNOLOGY DEVELOPMENT CO., LTD.
Reel/Frame 061571/0764 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 22, 2014
From: CHOI, MINHO; PARK, HYUNJUNG; CHOI, JUNGHOON
To: LG ELECTRONICS INC.
Reel/Frame 032729/0254 →
Priority Claims (1)
KR 10-2013-0044982 · Apr 23, 2013 · national
Continuity (1)
Related Publication 20140311567A1 · Oct 23, 2014