IP Library Granted Patent US 9,288,084
Granted Patent B1
US 9,288,084 · App. 14/259,338 · Granted Mar 15, 2016

Soft decision assisted equalizer adaptation

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Quick Facts
Patent No.
US 9,288,084
App. No.
14/259,338
Granted
Mar 15, 2016
Kind
B1
Abstract

A data processing system includes an equalizer circuit operable to equalize digital data according to tap coefficients to yield equalized data, a tap coefficient adaptation circuit operable to adapt the tap coefficients based at least in part on a scaled error signal, a data detector operable to apply a data detection algorithm to the digital data to generate hard decisions and soft decisions, an error calculation circuit operable to calculate an error signal based on the equalized data and on the hard decisions, and a scaling circuit operable to scale the error signal based on the soft decisions to yield the scaled error signal.

Claims (40)

1. A data processing system comprising:

an equalizer circuit operable to equalize digital data according to tap coefficients to yield equalized data;

a tap coefficient adaptation circuit operable to adapt the tap coefficients based at least in part on a scaled error signal;

a data detector operable to apply a data detection algorithm to the digital data to generate hard decisions and soft decisions;

an error calculation circuit operable to calculate an error signal based on the equalized data and on the hard decisions; and

a scaling circuit operable to scale the error signal based on the soft decisions to yield the scaled error signal.

2. The data processing system of claim 1 , wherein the equalizer circuit comprises a digital finite impulse response filter.

3. The data processing system of claim 1 , further comprising a second equalizer circuit operable to equalize the digital data to yield second equalized data, wherein the data detector is operable to apply the data detection algorithm to the second equalized data to generate the hard decisions and the soft decisions.

4. The data processing system of claim 1 , wherein the error calculation circuit comprises:

a convolution circuit operable to convolve the hard decisions with a partial response target to yield ideal digital data; and

a subtraction circuit operable to subtract the ideal digital data from the equalized data to yield the error signal.

5. The data processing system of claim 1 , wherein the scaling circuit comprises a multiplier operable to scale the error signal to yield the scaled error signal based on the soft decisions.

6. The data processing system of claim 5 , wherein the scaling circuit further comprises a comparator operable to compare the soft decisions with a threshold.

7. The data processing system of claim 6 , wherein the scaling circuit further comprises a weights circuit operable to provide a weight to the multiplier, wherein the multiplier is operable to scale the error signal by the weight, wherein the weight is based on an output of the comparator.

8. The data processing system of claim 6 , wherein the scaling circuit further comprises a minimum likelihood calculator operable to provide to the comparator a lowest likelihood value for a plurality of successive ones of the soft decisions.

9. The data processing system of claim 8 , wherein the minimum likelihood calculator is operable to output the lowest likelihood value for a same number of successive ones of the soft decisions as a number of elements in a partial response target used by the error calculation circuit.

10. The data processing system of claim 8 , wherein the minimum likelihood calculator is operable to output the lowest likelihood value for three successive ones of the soft decisions.

11. The data processing system of claim 1 , wherein the soft decisions comprise log likelihood ratio values.

12. The data processing system of claim 1 , further comprising a second data detector and a decoder operable to determine correct values of the equalized data.

13. The data processing system of claim 1 , wherein the data processing system is incorporated in a storage device.

14. The data processing system of claim 1 , wherein the data processing system is incorporated in a data transmission device.

15. A method for processing data comprising:

applying a data detection algorithm to detect values in digital data, yielding hard decisions and soft decisions;

equalizing the digital data according to tap coefficients to yield equalized data;

adapting the tap coefficients based at least in part on a scaled error signal;

calculating an error signal based on the equalized data and on the hard decisions; and

scaling the error signal based on the soft decisions to yield the scaled error signal.

16. The method of claim 15 , wherein scaling the error signal comprises selecting a weight and multiplying the error signal by the weight to yield the scaled error signal.

17. The method of claim 16 , wherein scaling the error signal further comprises identifying a minimum likelihood among a number of successive ones of the soft decisions.

18. The method of claim 17 , wherein scaling the error signal further comprises comparing the minimum likelihood with a threshold and selecting the weight based on the comparison.

19. The method of claim 15 , wherein calculating the error signal comprises convolving the hard decisions with a partial response target to yield ideal data, and subtracting the ideal data from the equalized data to yield the error signal.

20. A storage system comprising:

a storage medium maintaining a data set;

a read/write head assembly operable to provide an analog signal based on the data set on the storage medium;

an analog to digital converter operable to sample the analog signal to provide digital data;

an equalizer circuit operable to equalize the digital data according to tap coefficients to yield equalized data;

a tap coefficient adaptation circuit operable to adapt the tap coefficients based at least in part on a scaled error signal;

a data detector operable to apply a data detection algorithm to the digital data to generate hard decisions and soft decisions;

an error calculation circuit operable to calculate an error signal based on the equalized data and on the hard decisions; and

a scaling circuit operable to scale the error signal based on the soft decisions to yield the scaled error signal.

Assignments (10)
MERGER Recorded Mar 3, 2023
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; BROADCOM INTERNATIONAL PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 062952/0850 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2020
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
To: BROADCOM INTERNATIONAL PTE. LTD.
Reel/Frame 053771/0901 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047422 FRAME: 0464. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0702 →
MERGER Recorded Oct 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047422/0464 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 23, 2014
From: LU, LU; XIA, HAITAO; ZHANG, HAOTIAN; HUANG, JIANZHONG
To: LSI CORPORATION
Reel/Frame 032735/0640 →