Method and system for a pseudo-differential low-noise amplifier at Ku-band
View Patent ↗Methods and systems for a pseudo-differential low-noise amplifier at Ku-band may comprise a low-noise amplifier (LNA) integrated on a semiconductor die, where the LNA comprises differential pair transistors with an embedded inductor tail integrated on the semiconductor die. The embedded inductor tail may comprise: a first inductor with a first terminal capacitively-coupled to a gate terminal of a first transistor of the differential pair transistors and a second terminal of the first inductor coupled to second, third, and fourth inductors. The second inductor may be coupled to a source terminal of the first transistor of the differential pair transistors, the fourth inductor may be coupled to a source terminal of the second transistor of the differential pair transistors, and the third inductor may be capacitively-coupled to a gate terminal of the second transistor of the differential pair transistors and also to ground. The second inductor may be embedded within the first inductor.
1. A semiconductor device, the device comprising:
a low-noise amplifier (LNA) integrated on a semiconductor die, the LNA comprising differential pair transistors with an embedded inductor tail integrated on the semiconductor die, wherein the embedded inductor tail comprises:
a first inductor with a first terminal capacitively-coupled to a gate terminal of a first transistor of the differential pair transistors and a second terminal of the first inductor coupled to second, third, and fourth inductors, wherein the second inductor is coupled to a source terminal of the first transistor of the differential pair transistors, the fourth inductor is coupled to a source terminal of the second transistor of the differential pair transistors, and the third inductor is capacitively-coupled to a gate terminal of the second transistor of the differential pair transistors and also to ground.
2. The device according to claim 1 , wherein the second inductor is embedded within the first inductor.
3. The device according to claim 1 , wherein the fourth inductor is embedded within the third inductor.
4. The device according to claim 1 , wherein cascode transistors are coupled to drain terminals of the differential pair transistors.
5. The device according to claim 4 , wherein the cascode transistors have inductive loads comprising inductors integrated on the semiconductor die.
6. The device according to claim 4 , wherein the differential pair transistors and the cascode transistors comprise complementary metal-oxide semiconductor (CMOS) transistors.
7. The device according to claim 1 , wherein the first inductor is capacitively-coupled to the gate of the first transistor of the differential pair transistors and the fourth inductor is capacitively-coupled to the gate of the second transistor of the differential pair transistors utilizing CMOS capacitors.
8. The device according to claim 1 , wherein the LNA is operable to receive a single-ended signal and generate a differential output signal.
9. The device according to claim 1 , wherein the embedded inductor tail is operable to provide electro-static discharge (ESD) protection for the LNA.
10. The device according to claim 1 , wherein the semiconductor die is bonded to a packaging substrate.
11. A method for communication, the method comprising:
in a low-noise amplifier (LNA) integrated on a semiconductor die, the LNA comprising differential pair transistors with an embedded inductor tail integrated on the semiconductor die, amplifying a radio frequency (RF) signal, wherein the embedded inductor tail comprises:
a first inductor with a first terminal capacitively-coupled to a gate terminal of a first transistor of the differential pair transistors and a second terminal of the first inductor coupled to second, third, and fourth inductors, wherein the second inductor is coupled to a source terminal of the first transistor of the differential pair transistors, the fourth inductor is coupled to a source terminal of the second transistor of the differential pair transistors, and the third inductor is capacitively-coupled to a gate terminal of the second transistor of the differential pair transistors and also to ground.
12. The method according to claim 11 , wherein the second inductor is embedded within the first inductor.
13. The method according to claim 11 , wherein the fourth inductor is embedded within the third inductor.
14. The method according to claim 11 , wherein cascode transistors are coupled to drain terminals of the differential pair transistors.
15. The method according to claim 14 , wherein the cascode transistors have inductive loads comprising inductors integrated on the semiconductor die.
16. The method according to claim 14 , wherein the differential pair transistors and the cascode transistors comprise complementary metal-oxide semiconductor (CMOS) transistors.
17. The method according to claim 11 , wherein the first inductor is capacitively-coupled to the gate of the first transistor of the differential pair transistors and the fourth inductor is capacitively-coupled to the gate of the second transistor of the differential pair transistors utilizing CMOS capacitors.
18. The method according to claim 17 , comprising generating a differential output signal from the received RF signal using the LNA.
19. The method according to claim 11 , comprising electro-static discharge (ESD) protection for the LNA utilizing the embedded inductor tail.
20. A semiconductor device comprising:
a low-noise amplifier (LNA) integrated on a complementary metal-oxide semiconductor (CMOS) die, the LNA comprising differential pair transistors with an embedded inductor tail integrated on the semiconductor die, wherein the embedded inductor tail comprises:
a first inductor with a first terminal capacitively-coupled to a gate terminal of a first transistor of the differential pair transistors and a second terminal of the first inductor coupled to second, third, and fourth inductors, wherein the second inductor is coupled to a source terminal of the first transistor of the differential pair transistors, the fourth inductor is coupled to a source terminal of the second transistor of the differential pair transistors, the third inductor is capacitively-coupled to a gate terminal of the second transistor of the differential pair transistors and also to ground, and wherein a differential output of the LNA is provided at drain terminals of cascode transistors coupled to drain terminals of the differential pair transistors.