Semi-automatic restructuring of offloadable tasks for accelerators

1. A computer implemented method comprising:

identifying code regions in an application from which one or more offloadable tasks can be generated by a compiler for a heterogenous computing system including a processor and an accelerator memory, comprising:

adding, by the processor, relaxed semantics to a directive based language in the heterogenous computing system for allowing a user to suggest rather than specify a parallel code region as an offloadable task candidate, wherein the offloadable task candidate is a sub-offload or a super-offload; and

identifying, by the processor, one or more offloadable tasks in a neighborhood of code region marked by the directive based language.

2. The computer implemented method of claim 1 , wherein the sub-offload comprises only part of the neighborhood of code region marked by the directive based language is offloaded to the accelerator memory while the other part of the neighborhood of code region executes on the processor in parallel.

3. The computer implemented method of claim 1 , wherein the sub-offload comprises splitting an index range of a main parallel loop into two or more sub-loops and declaring one of the two or more sub-loops as the offloadable task candidate.

4. The computer implemented method of claim 1 , wherein the sub-offload comprises handling reduction variables and critical sections across sub-loops without additional synchronization.

5. The computer implemented method of claim 1 , wherein the sub-offload comprises enabling concurrent execution of a task on the processor and the accelerator memory.

6. The computer implemented method of claim 1 , wherein the super-offload comprises declaring a code region larger than a code region specified by a developer as the offloadable task candidate.

7. The computer implemented method of claim 6 , wherein the super-offload comprises reducing data transfers between the processor and the accelerator memory.

8. A heterogenous computing system comprising:

a processor;

an accelerator memory; and

a compiler that identifies code regions in an application from which one or more offloadable tasks can be generated for the heterogenous computing system, wherein the identifying comprises:

adding relaxed semantics to a directive based language in the heterogenous computing system for allowing a user to suggest rather than specify a parallel code region as an offloadable task candidate, wherein the offloadable task candidate is a sub-offload or a super-offload; and

identifying one or more offloadable tasks in a neighborhood of code region marked by the directive based language.

9. The heterogenous computing system of claim 8 , wherein the sub-offload comprises only part of the neighborhood of code region marked by the directive based language is offloaded to the accelerator memory while the other part of the neighborhood of code region executes on the processor in parallel.

10. The heterogenous computing system of claim 8 , wherein the sub-offload comprises splitting an index range of a main parallel loop into two or more sub-loops and declaring one of the two or more sub-loops as the offloadable task candidate.

11. The heterogenous computing system of claim 8 , wherein the sub-offload comprises handling reduction variables and critical sections across sub-loops without additional synchronization.

12. The heterogenous computing system of 8 , wherein the sub-offload comprises enabling concurrent execution of a task on the processor and the accelerator memory.

13. The heterogenous computing system of claim 8 , wherein the super-offload comprises declaring a code region larger than a code region specified by a developer as the offloadable task candidate.

14. The heterogenous computing system of claim 13 , wherein the super-offload comprises reducing data transfers between the processor and the accelerator memory.