IP Library Granted Patent US 9,219,126
Granted Patent B2
US 9,219,126 · App. 14/262,491 · Granted Dec 22, 2015

High-k dielectrics with a low-k interface for solution processed devices

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,219,126
App. No.
14/262,491
Granted
Dec 22, 2015
Kind
B2
Abstract

A device, including a substrate, an electronically active component on the substrate, an interface dielectric on the semiconductor, and a relaxor dielectric on the interface dielectric. The relaxor dielectric includes a surfactant that is solid at room temperature.

Claims (32)

1. A device, comprising:

a substrate;

an electronically active component on the substrate;

an interface dielectric at least partially on the electrically active component; and

a relaxor dielectric on the interface dielectric, wherein the relaxor dielectric includes a surfactant that is solid at room temperature and has a higher dielectric constant than the interface dielectric.

2. The device of claim 1 , further comprising a source and a drain on the substrate at least partially covered by the electronically active layer, and the electronically active layer comprises a semiconductor.

3. The device of claim 2 , further comprising a gate on the interface dielectric.

4. The device of claim 1 , wherein the interface dielectric comprises one of a dielectric or a nanoparticle blend.

5. The device of claim 1 , wherein the interface dielectric comprises a perfluoropolymer.

6. The device of claim 1 , wherein the interface dielectric comprises a high-k PVDF-copolymer.

7. The device of claim 1 , wherein the surfactant comprises a methacrylate-based fluorinated copolymer.

8. The device of claim 1 , wherein the surfactant and the interface dielectric are soluble in the same solvents.

9. The device of claim 1 , wherein the surfactant concentration in the interface dielectric is low enough to allow for further solution processing and high enough to allow formation of a film on the surface of the dielectric.

10. The device of claim 1 , wherein the electronically active layer comprises a metal electrode.

11. The device of claim 8 , wherein the device further comprises a capacitor having a second electrode on the interface dielectric.

12. A method of manufacturing an electronic device, comprising:

forming an electronically active component on a substrate;

printing an interface dielectric over the electronically active component;

mixing a solid surfactant with a second dielectric; and

printing the second dielectric onto the interface dielectric.

13. The method of claim 10 , wherein forming an electronically active component comprises forming a source and drain on the substrate.

14. The method of claim 13 , further comprising forming a gate on the interface dielectric.

15. The method of claim 12 , wherein forming an electronically active component comprises forming a metal electrode on the substrate.

16. The method of claim 15 , further comprising forming a second electrode on the interface dielectric.

17. The method of claim 12 , wherein printing an interface dielectric comprises printing a perfluopolymer.

18. The method of claim 11 , wherein mixing a solid surfactant with a dielectric, comprises mixing one of trifluorotoluene, n-methyl-2-pyrrolidone, methyl ethyl ketone, and toluene, with one of poly(methylmethacrylate), cyanoethyl pullulan, P(VDF-TrFE-CFE), P(VDF-TrFE-CTFE), and polystyrene.

19. A device, comprising:

a substrate;

a source and a drain on the substrate;

an electronically active component comprising a semiconductor on the substrate at least partially covering the source and drain;

an interface dielectric on the electrically active component; and

a relaxor dielectric on the interface dielectric, wherein the relaxor dielectric includes a surfactant that is solid at room temperature.

Assignments (10)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 6, 2025
From: XEROX CORPORATION
To: GENESEE VALLEY INNOVATIONS, LLC
Reel/Frame 073842/0479 →
SECOND LIEN NOTES PATENT SECURITY AGREEMENT Recorded Jul 2, 2025
From: XEROX CORPORATION
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 071785/0550 →
FIRST LIEN NOTES PATENT SECURITY AGREEMENT Recorded Apr 11, 2025
From: XEROX CORPORATION
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 070824/0001 →
SECURITY INTEREST Recorded Feb 13, 2024
From: XEROX CORPORATION
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 066741/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT RF 064760/0389 Recorded Feb 13, 2024
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: XEROX CORPORATION
Reel/Frame 068261/0001 →
SECURITY INTEREST Recorded Nov 20, 2023
From: XEROX CORPORATION
To: JEFFERIES FINANCE LLC, AS COLLATERAL AGENT
Reel/Frame 065628/0019 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVAL OF US PATENTS 9356603, 10026651, 10626048 AND INCLUSION OF US PATENT 7167871 PREVIOUSLY RECORDED ON REEL 064038 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jun 28, 2023
From: PALO ALTO RESEARCH CENTER INCORPORATED
To: XEROX CORPORATION
Reel/Frame 064161/0001 →
SECURITY INTEREST Recorded Jun 22, 2023
From: XEROX CORPORATION
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 064760/0389 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 20, 2023
From: PALO ALTO RESEARCH CENTER INCORPORATED
To: XEROX CORPORATION
Reel/Frame 064038/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 25, 2014
From: WHITING, GREGORY; NG, TSE NGA; HSIEH, BING R.
To: PALO ALTO RESEARCH CENTER INCORPORATED
Reel/Frame 032762/0118 →