FinFET with a single contact to multiple fins bridged together to form a source/drain region of the transistor

1. A semiconductor device comprising:

a semiconductor substrate with a first semiconductor fin with a first protrusion and a second semiconductor fin with a second protrusion, the first semiconductor fin being adjacent the second semiconductor fin, the first and second semiconductor fins extending in a first direction;

a gate electrode extending in a second direction and positioned over the first protrusion of the first semiconductor fin and over the second protrusion of the second semiconductor fin;

a first source/drain adjacent the first protrusion and extending from the first semiconductor fin, an upper oblique surface of the first source/drain and a lower oblique surface of the first source/drain meeting at a first corner of the first source/drain;

a second source/drain adjacent the second protrusion and extending from the second semiconductor fin, an upper oblique surface of the second source/drain and a lower oblique surface of the second source/drain meeting at a second corner of the second source/drain,

a semiconductor bridge extending between and contacting the first corner of the first source/drain and the second corner of the second source/drain,

wherein the semiconductor bridge includes a first portion at the first corner and the second corner and a second portion on the first portion extending between and contacting the upper oblique surface of the first source/drain and the upper oblique surface of the second source/drain, and

wherein the upper oblique surface of the first source/drain intersects the upper oblique surface of the second source/drain.

2. The semiconductor device of claim 1 , wherein the first portion of the semiconductor bridge is located at the intersection of the upper oblique surfaces of the first and second source drains.

3. The semiconductor device off claim 2 ,

wherein the lower oblique surface of the first source/drain intersects the lower oblique surface of the second source/drain, and

wherein the semiconductor device further comprises a capping layer on the lower oblique surfaces of the first and second drains, extending to the intersection of the lower oblique surfaces.

4. A semiconductor device comprising:

a semiconductor substrate with a first semiconductor fin with a first protrusion and a second semiconductor fin with a second protrusion, the first semiconductor fin being adjacent the second semiconductor fin, the first and second semiconductor fins extending in a first direction;

a gate electrode extending in a second direction and positioned over the first protrusion of the first semiconductor fin and over the second protrusion of the second semiconductor fin;

a first source/drain adjacent the first protrusion and extending from the first semiconductor fin, an upper oblique surface of the first source/drain and a lower oblique surface of the first source/drain meeting at a first corner of the first source/drain;

a second source/drain adjacent the second protrusion and extending from the second semiconductor fin, an upper oblique surface of the second source/drain and a lower oblique surface of the second source/drain meeting at a second corner of the second source/drain;

a semiconductor bridge extending between and contacting the first corner of the first source/drain and the second corner of the second source/drain;

a third semiconductor fin with a third protrusion and a fourth semiconductor fin with a fourth protrusion, the third semiconductor fin being adjacent the fourth semiconductor fin;

a second gate electrode extending over the third protrusion of the third semiconductor fin and over the fourth protrusion of the fourth semiconductor fin;

a third source/drain adjacent the third protrusion and extending from the third semiconductor fin, an upper oblique surface of the third source/drain and a lower oblique surface of the third source drain meeting at a third corner of the third source/drain;

a fourth source/drain adjacent the fourth protrusion and extending from the fourth semiconductor fin, an upper oblique surface of the fourth source/drain and a lower oblique surface of the fourth source drain meeting at a fourth corner of the fourth source/drain;

an interlayer dielectric layer disposed about the first and second source/drains and below the semiconductor bridge; and

a conductive contact extending through the interlayer dielectric, the conductive contact comprising a silicide layer contacting the semiconductor bridge at an upper surface of the semiconductor bridge.

5. The semiconductor device of claim 4 , wherein a pitch distance between the first fin and the second fin is 48 nm or less.

6. The semiconductor device of claim 4 ,

wherein the first semiconductor fin, the second semiconductor fin, the first source/drain and the second source drain are located in a logic region of the semiconductor device, and

wherein the third semiconductor fin, the fourth semiconductor fin, the third source/drain and the fourth source/drain are located in a memory region of the semiconductor device.

7. The memory device of claim 6 , wherein the memory region is an SRAM region.

8. A semiconductor device comprising:

a semiconductor substrate with a first semiconductor fin with a first protrusion and a second semiconductor fin with a second protrusion, the first semiconductor fin being adjacent the second semiconductor fin, the first and second semiconductor fins extending in a first direction;

a gate electrode extending in a second direction and positioned over the first protrusion of the first semiconductor fin and over the second protrusion of the second semiconductor fin;

a first source/drain adjacent the first protrusion and extending from the first semiconductor fin, an upper oblique surface of the first source/drain and a lower oblique surface of the first source/drain meeting at a first corner of the first source/drain;

a second source/drain adjacent the second protrusion and extending from the second semiconductor fin, an upper oblique surface of the second source/drain and a lower oblique surface of the second source/drain meeting at a second corner of the second source/drain;

a semiconductor bridge extending between and contacting the first corner of the first source/drain and the second corner of the second source/drain;

an interlayer dielectric layer disposed about the first and second source/drains and below the semiconductor bridge; and

a conductive contact extending through the interlayer dielectric, the conductive contact comprising a silicide layer contacting the semiconductor bridge at an upper surface of the semiconductor bridge.

9. The semiconductor device of claim 8 ,

wherein the first and second source/drains contact the first and second fins at a first height,

wherein, at the first height, the first fin and the second fin are separated from each other by a first distance,

wherein a minimum distance between the first source/drain and the second source/drain is between the first corner of the first source/drain and the second source/drain, the minimum distance being less than the first distance.

10. The semiconductor device of claim 8 ,

wherein the first and second source/drains contact the first and second fins at a first height,

wherein, at the first height, the first fin and the second fin are separated from each other by a first distance, and

wherein, with respect to a cross section taken in a direction perpendicular to the first direction, the width of the conductive contact is greater than the first distance.

11. The semiconductor device of claim 8 , wherein, with respect to a cross section taken in a direction perpendicular to the first direction, the first and second source/drains have a diamond shape.

12. The semiconductor device of claim 8 , further comprising an air gap in the interlayer dielectric at a location under the semiconductor bridge.

13. The semiconductor device of claim 8 , wherein at least a portion of the semiconductor bridge has a doping concentration higher than a doping concentration of the first and second source/drains.

14. The semiconductor device of claim 8 ,

wherein the lower oblique surface of the first source/drain intersects the lower oblique surface of the second source/drain, and

wherein the semiconductor device further comprises a capping layer on the lower oblique surfaces of the first and second drains, extending to the intersection of the lower oblique surfaces.

15. The semiconductor device of claim 8 , further comprising an epitaxial semiconductor capping layer formed on a bottom surface of the semiconductor bridge and above the interlayer dielectric.

16. The semiconductor device of claim 8 , wherein the semiconductor bridge includes a first portion at the first corner and the second corner and a second portion on the first portion extending between and contacting the upper oblique surface of the first source/drain and the upper oblique surface of the second source/drain.

17. The semiconductor device of claim 16 , wherein the second portion of the semiconductor bridge has a top surface at least as high as top surfaces of the first and second source/drains.

18. The semiconductor device of claim 16 , wherein the first portion of the semiconductor bridge extends between and contacts the first corner and the second corner and extends between and contacts the lower oblique surfaces of the first and second source/drains.

19. The semiconductor device of claim 16 , wherein a doping concentration of the first portion of the semiconductor bridge is higher than a doping concentration of the second portion of the semiconductor bridge.

20. The semiconductor device of claim 19 , wherein a doping concentration of the first portion of the bridge is higher than a doping concentration of the first and second source/drains.