NAND string utilizing floating body memory cell
NAND string configurations and semiconductor memory arrays that include such NAND string configurations are provided. Methods of making semiconductor memory cells used in NAND string configurations are also described.
1. A semiconductor memory cell comprising:
a floating body region configured to be charged to a level indicative of a state of the memory cell, said floating body region have a first conductivity type selected from p-type conductivity type and n-type conductivity type;
said floating body region having a bottom surface bounded by an insulator layer;
a first region in electrical contact with said floating body region, said first region exposed at or proximal to a top surface of said floating body region and extending to contact said insulator layer;
a second region in electrical contact with said floating body region and spaced apart from said first region, said second region exposed at or proximal to said top surface of said floating body region and extending into said floating body region, wherein said floating body region underlies said second region such that said second region does not extend to contact said insulator layer;
a third region in electrical contact with said floating body region and spaced apart from said first and second regions, said third region exposed at or proximal to said top surface of said floating body region and extending to contact said insulator layer; and
a gate positioned between said first and second regions;
wherein said third region is configured to function as a collector region to maintain a charge of said floating body region, thereby maintaining said state of said floating body region; and
wherein said semiconductor memory cell has only one said gate.
2. The semiconductor memory cell of claim 1 , wherein said floating body is formed in a substrate having said first conductivity type and said insulator is a buried layer positioned between said bottom surface of said floating body region and a lower portion of said substrate.
3. The semiconductor memory cell of claim 2 , wherein said top surface of said floating body region is a top surface of said substrate.
4. The semiconductor memory cell of claim 1 , wherein said first, second and third regions have a second conductivity type selected from said p-type conductivity type and said n-type conductivity type, and wherein said second conductivity type is different from said first conductivity type.
5. The semiconductor memory cell of claim 1 , wherein said first and third regions electrically isolate said floating body region from neighboring floating body regions of adjacent ones of said semiconductor memory cell when a plurality of said semiconductor memory cells are joined in an array.
6. The semiconductor memory cell of claim 1 , wherein said floating body region and said first, second and third regions are provided in a fin structure that extends vertically above said insulator layer.