Semiconductor device having CAL latency function
A method for accessing a semiconductor device having a memory array, the method includes receiving a mode register command to set a command latency value in a mode register, receiving a chip select signal, activating a command receiver in response to the chip select signal, receiving, with the command receiver, an access command with a first latency from the chip select signal equal to the command latency value, accessing the memory array in response to the access command, and deactivating the command receiver with a second latency from the chip select signal equal to a deactivation latency value.
1. A method for accessing a semiconductor device having a memory array, the method comprising:
receiving a mode register command to set a command latency value in a mode register;
receiving a chip select signal;
activating a command receiver in response to the chip select signal;
receiving, with the command receiver, an access command with a first latency from the chip select signal equal to the command latency value;
accessing the memory array in response to the access command; and
deactivating the command receiver with a second latency from the chip select signal equal to a deactivation latency value.
2. The method as claimed in claim 1 wherein the mode register command includes a set value to enable the command latency value.
3. The method as claimed in claim 2 wherein the command receiver is constantly activated if the set value is disabled.
4. The method as claimed in claim 1 wherein an address receiver is enabled and disabled at same times as the command receiver and, with a third latency from the chip select signal equal to the command latency value, an access address is received with the address receiver.
5. The method as claimed in claim 1 wherein the access command is an active command.
6. The method as claimed in claim 1 wherein the access command is a read command.
7. The method as claimed in claim 1 wherein the access command is a write command.
8. The method as claimed in claim 1 wherein the access command is a precharge command.
9. The method as claimed in claim 1 wherein the command latency value is 3 clock cycles.
10. The method as claimed in claim 9 wherein the deactivation latency value is 8 clock cycles.
11. The method as claimed in claim 1 wherein the deactivation latency value is greater than the command latency value.
12. The method as claimed in claim 1 further comprising:
receiving an additional chip select signal after the receiving of the chip select signal and before the deactivating of the command receiver;
receiving, with the command receiver, an additional access command with a third latency from the additional chip select signal equal to the command latency value;
accessing the memory array in response to the additional access command; and
deactivating the command receiver with a fourth latency from the additional chip select signal equal to the deactivation latency value.
13. The method for accessing a semiconductor device as claimed in claim 1 wherein the semiconductor device is a Double Data Rate Dynamic Random Access Memory.