IP Library Patent Application 14271588
Patent Application
App. No. 14/271,588

STORAGE SYSTEM HAVING FIFO STORAGE AND RESERVED STORAGE

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Quick Facts
Patent No.
US None
App. No.
14/271,588
Abstract

An apparatus having first-in-first-out storage and reserved storage is disclosed. In one or more embodiments, the apparatus includes memory circuitry having first-in-first-out storage and reserved storage. The first-in-first-out storage and the reserved storage include an array of data elements having contiguous addresses across the first-in-first-out storage and the reserved storage. The memory circuitry includes a first-in-first-out pointer for referencing an index corresponding to a data element of the array of data elements of the first-in-first-out storage to be read and a read pointer mapped to the first-in-first-out pointer and for referencing a memory location of the data element to be read. The read pointer is mapped such that the read pointer does not reference a plurality of data elements stored in the reserved storage.

Claims (28)

1 . An apparatus comprising:

memory circuitry having first-in-first-out storage and reserved storage, the first-in-first-out storage and the reserved storage including an array of data elements having contiguous addresses across the first-in-first-out storage and the reserved storage, the memory circuitry including a first-in-first-out pointer configured to reference an index corresponding to at least one data element of the array of data elements of the first-in-first-out storage to be read, the memory circuitry including a read pointer mapped to the first-in-first-out pointer and configured to reference a memory location of the data element to be read,

wherein the read pointer is mapped such that the read pointer does not reference a plurality of data elements stored in the reserved storage.

2 . The apparatus as recited in claim 1 , further comprising a barrel shifter communicatively connected to the memory circuitry for receiving a data block from the first-in-first-out storage during a read operation.

3 . The apparatus as recited in claim 1 , wherein the read pointer identifies a row address of a next row to be read from the memory circuitry.

4 . The apparatus as recited in claim 1 , wherein the data element to be read stores a data block.

5 . The apparatus as recited in claim 4 , wherein the data block comprises a data block of a fixed-width.

6 . The apparatus as recited in claim 1 , wherein the memory circuitry is implemented as an integrated circuit.

7 . The apparatus as recited in claim 1 , wherein the memory circuitry is incorporated in a storage device.

8 . The apparatus as recited in claim 7 , wherein the storage device comprises a redundant array of independent disks.

9 . A system comprising:

memory circuitry having first-in-first-out storage and reserved storage, the first-in-first-out storage and the reserved storage including an array of data elements having contiguous addresses across the first-in-first-out storage and the reserved storage, the memory circuitry including a first-in-first-out pointer configured to reference an index corresponding to at least one data element of the array of data elements of the first-in-first-out storage to be read; and

an index updating module configured to receive the first-in-first-out pointer and generate a read pointer, the read pointer mapped to the first-in-first-out pointer and configured to reference a memory location of the data element to be read, wherein the read pointer is mapped such that the read pointer does not reference a plurality of data elements stored in the reserved storage.

10 . The system as recited in claim 9 , further comprising a barrel shifter communicatively connected to the memory circuitry for receiving a data block from the first-in-first-out storage during a read operation.

11 . The system as recited in claim 9 , wherein the read pointer identifies a row address of a next row to be read from the memory circuitry.

12 . The system as recited in claim 9 , wherein the data element to be read stores a data block.

13 . The system as recited in claim 12 , wherein the data block comprises a data block of a fixed-width.

14 . The system as recited in claim 9 , wherein the memory circuitry is implemented as an integrated circuit.

15 . The system as recited in claim 9 , wherein the memory circuitry is incorporated in a storage device.

16 . The system as recited in claim 15 , wherein the storage device comprises a redundant array of independent disks.

17 . A method comprising:

receiving a command to initiate a read operation at a storage device, the storage device including first-in-first-out storage and reserved storage, the first-in-first-out storage and the reserved storage including an array of data elements having contiguous addresses across the first-in-first-out storage and the reserved storage, the array of data elements for storing data blocks;

furnishing a data block referenced by a read pointer to a barrel shifter, the data block stored in the first-in-first-out storage;

updating a first-in-first-out pointer based upon the read operation, the first-in-first-out pointer for referencing an index corresponding to at least one data element of the array of data elements of the first-in-first-out storage to be read; and

mapping a read pointer to the first-in-first-out pointer such that the read pointer does not reference a plurality of data elements stored in the reserved storage.

18 . The method as recited in claim 17 , wherein the read pointer identifies a row address of a next row to be read from the memory circuitry.

19 . The method as recited in claim 17 , wherein the data element to be read stores a data block.

20 . The method as recited in claim 19 , wherein the data block comprises a data block of a fixed-width.

Assignments (4)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 7, 2014
From: GUO, XIANGDONG; LI, ZHIBIN; WU, ZHIWEI; SHEN, RUI
To: LSI CORPORATION
Reel/Frame 032838/0711 →