Vertically-integrated nonvolatile memory devices having laterally-integrated ground select transistors
Nonvolatile memory devices utilize vertically-stacked strings of nonvolatile memory cells (e.g., NAND-type strings) that can be selectively coupled to common source lines within a substrate. This selective coupling may be provided by lateral ground select transistors having different threshold voltages that account for different lateral spacings between the vertically-stacked strings of nonvolatile memory cells and the common source lines.
1. A nonvolatile memory device comprising:
first and second common source lines of a first conductivity type in a substrate;
a channel region of a second conductivity type in the substrate between the first and second common source lines;
a stacked structure on the channel region, the stacked structure including a vertically-stacked plurality of conductive patterns;
first and second string selection lines on the stacked structure, the first and second string selection lines horizontally spaced apart from each other;
a bit line overlapping the first and second string selection lines;
a first vertical channel penetrating the first string selection line and the stacked structure, the first vertical channel connecting the first common source line to the bit line; and
a second vertical channel penetrating the second string selection line and the stacked structure, the second vertical channel connecting the second common source line to the bit line.
2. The nonvolatile memory device of claim 1 , wherein each of the first and second vertical channels is in contact with the channel region.
3. The nonvolatile memory device of claim 1 ,
wherein the first vertical channel is spaced apart from the first common source line by a first distance, and
wherein the second vertical channel is spaced apart from the second common source line by a second distance different from the first distance.
4. The nonvolatile memory device of claim 1 ,
wherein the channel region comprises edge regions directly adjacent the first and second common source lines and a middle region between the edge regions, and
wherein a first impurity doping concentration of the edge regions is higher than a second impurity doping concentration of the middle region.
5. The nonvolatile memory device of claim 4 , the first and second vertical channels are in contact with the middle region.
6. The nonvolatile memory device of claim 4 , wherein the middle region comprises:
first regions contacting the first and second vertical channels, and extending in a direction; and
a second region extending in the direction between the first regions.
7. The nonvolatile memory device of claim 4 , wherein the middle region comprises a doping region extending in a direction between the first and second vertical channels and having the second conductivity type.
8. The nonvolatile memory device of claim 1 , wherein the first and second common source lines are substantially parallel with the first and the second string selection lines.
9. A nonvolatile memory device comprising:
first and second common source lines of a first conductivity type in a substrate;
a channel region of a second conductivity type in the substrate between the first and second common source lines;
a bit line overlapping the first and second common source lines;
a first string connected between the first common source line and the bit line, the first string comprising:
a first vertically-stacked plurality of nonvolatile memory cells;
a first string select transistor connected between the bit line and the first vertically-stacked plurality of nonvolatile memory cells;
a first ground select transistor connected with the first vertically-stacked plurality of nonvolatile memory cells; and
a first lateral ground select transistor connected between the first ground select transistor and the first common source line; and
a second string connected between the second common source line and the bit line, the second string comprising:
a second vertically-stacked plurality of nonvolatile memory cells;
a second string select transistor connected between the bit line and the second vertically-stacked plurality of nonvolatile memory cells;
a second ground select transistor connected with the second vertically-stacked plurality of nonvolatile memory cells; and
a second lateral ground select transistor connected between the second ground select transistor and the second common source line,
wherein the first and second lateral ground select transistors are configured to use the channel region as a channel.
10. The nonvolatile memory device of claim 9 ,
wherein the channel region comprises edge regions directly adjacent the first and second common source lines and a middle region between the edge regions, and
wherein a first impurity doping concentration of the edge regions is higher than a second impurity doping concentration of the middle region.
11. The nonvolatile memory device of claim 10 , wherein the first and second lateral ground select transistors are configured to use the edge regions as the channel.
12. The nonvolatile memory device of claim 10 ,
wherein the first string is spaced apart from the first common source line by a first distance, and
wherein the second string is spaced apart from the second common source line by a second distance different from the first distance.