Digital signal up-converting apparatus and related digital signal up-converting method
A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.
1. A digital signal up-converting apparatus, comprising:
a clock generating circuit, arranged to generate a reference clock signal;
an adjusting circuit, coupled to the clock generating circuit, arranged to generate a first clock signal and a plurality of second clock signals according to the reference clock signal;
a baseband circuit, coupled to the adjusting circuit, for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and
a sampling circuit, coupled to the adjusting circuit and the baseband circuit, for receiving the plurality of second clock signals and the digital output signal, wherein the plurality of second clock signals are non-overlapping;
wherein the sampling circuit samples the digital output signal based on at least one of the plurality of second clock signals and then combines the sampled digital output signal in order to generate a combined digital signal; and the first clock signal is a phase-adjusted clock signal of the reference clock signal and the at least one of the plurality of second clock signals is a duty cycle-adjusted clock signal of the reference clock signal, wherein the duty cycle-adjusted clock signal is between 0% and 100%, non-inclusive.
2. The digital signal up-converting apparatus of claim 1 , further comprising:
an amplifier, arranged to generate an amplified output signal according to the combined digital signal.
3. The digital signal up-converting apparatus of claim 1 , wherein the adjusting circuit comprises:
a phase adjusting circuit, arranged to adjust a phase of the reference clock signal to generate the first clock signal; and
a duty cycle adjusting circuit, arranged to adjust a duty cycle of the reference clock signal to generate the plurality of second clock signals.
4. The digital signal up-converting apparatus of claim 1 , wherein the baseband circuit is arranged to delay a baseband data to generate the digital output signal according to the first clock signal.
5. The digital signal up-converting apparatus of claim 1 , wherein signal edges of the plurality of second clock signals are non-overlapping.
6. A digital signal up-converting apparatus, comprising:
a clock generating circuit, arranged to generate a reference clock signal;
an adjusting circuit, coupled to the clock generating circuit, arranged to generate a first clock signal and a plurality of second clock signals according to the reference clock signal, wherein the adjusting circuit comprises:
a phase adjusting circuit, arranged to adjust a phase of the reference clock signal to generate the first clock signal; and
a duty cycle adjusting circuit, arranged to adjust a duty cycle of the reference clock signal to generate the plurality of second clock signals;
a baseband circuit, coupled to the adjusting circuit, for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and
a sampling circuit, coupled to the adjusting circuit and the baseband circuit, for receiving the plurality of second clock signals and the digital output signal, wherein the plurality of second clock signals are non-overlapping;
wherein the sampling circuit samples the digital output signal based on the plurality of second clock signals and then combines the sampled digital output signal in order to generate a combined digital signal.
7. The digital signal up-converting apparatus of claim 6 , further comprising:
an amplifier, arranged to generate an amplified output signal according to the combined digital signal.
8. The digital signal up-converting apparatus of claim 6 , wherein the baseband circuit is arranged to delay a baseband data to generate the digital output signal according to the first clock signal.
9. The digital signal up-converting apparatus of claim 6 , wherein signal edges of the plurality of second clock signals are non-overlapping.