Frame buffer power management
View Patent ↗For frame buffer power management, a frame buffer includes a write circuit and a read circuit, and drives a display. A power management module terminates power to the frame buffer in response to a power reduction policy being satisfied.
1. An apparatus comprising:
a frame buffer comprising a write circuit, magnetic random-access memory (MRAM) cells, and a read circuit and that drive a display, wherein the write circuit writes pixel values to the MRAM cells and the read circuit reads the pixel values from the MRAM cells; and
a power management module of semiconductor gates that terminates power to the write circuit and maintains power to the read circuit in response to a power reduction policy being satisfied, wherein the power reduction policy is satisfied in response to a last graphics input interval exceeding an input interval threshold and the last graphics input interval is a time interval from a no-pixel update signal.
2. The apparatus of claim 1 , wherein the power is terminated to a graphics adapter in response to the last graphics input interval exceeding the input interval threshold.
3. The apparatus of claim 1 , wherein the power reduction policy is satisfied in response to a device sleep signal and the power is terminated to the write circuit and the read circuit in response to the device sleep signal.
4. The apparatus of claim 1 , wherein the power management module further activates power to the frame buffer in response to a power activation policy being satisfied.
5. The apparatus of claim 4 , wherein the power activation policy is satisfied in response to a refresh time exceeding a refresh interval and the power management module activates power to the read circuit in response to the refresh time exceeding the refresh interval.
6. The apparatus of claim 4 , wherein the power activation policy is satisfied in response to a graphics input and the power management module activates power to the write circuit and the read circuit in response to the graphics input.
7. The apparatus of claim 4 , wherein the power activation policy is satisfied in response to a device wake signal and the power management module activates power to the write circuit and the read circuit in response to the device wake signal.
8. The apparatus of claim 1 , wherein the MRAM is spin torque transfer random access memory (STT-RAM).
9. A system comprising:
a graphics controller that generates pixel values;
a display that displays the pixel values;
a frame buffer comprising a write circuit, magnetic random-access memory (MRAM) cells, and a read circuit, and that drives the pixel values to the display, wherein the write circuit writes pixel values to the MRAM cells and the read circuit reads the pixel values from the MRAM cells; and
a power management module of semiconductor gates that terminates power to the write circuit and maintains power to the read circuit in response to a power reduction policy being satisfied, wherein the power reduction policy is satisfied in response to a last graphics input interval exceeding an input interval threshold and the last graphics input interval is a time interval from a no-pixel update signal.
10. The system of claim 9 , wherein the power reduction policy is satisfied in response to a device sleep signal and the power is terminated to the write circuit and the read circuit in response to the device sleep signal.
11. The system of claim 9 , the power management module further activating power to the frame buffer in response to a power activation policy being satisfied.
12. The system of claim 11 , wherein the power activation policy is satisfied in response to a refresh time exceeding a refresh interval and the power management module activates power to the read circuit in response to the refresh time exceeding the refresh interval.
13. A method comprising:
determining that a power reduction policy for a frame buffer is satisfied, the frame buffer comprising a write circuit, magnetic random-access memory (MRAM) cells, and a read circuit, and driving a display, wherein the write circuit writes pixel values to the MRAM cells and the read circuit reads the pixel values from the MRAM cells; and
terminating power to the write circuit and maintaining power to the read circuit in response to the power reduction policy being satisfied, wherein the power reduction policy is satisfied in response to a last graphics input interval exceeding an input interval threshold and the last graphics input interval is a time interval from a no-pixel update signal.
14. The method of claim 13 , wherein the power reduction policy is satisfied in response to a device sleep signal and the method terminating power to the write circuit and the read circuit in response to the device sleep signal.
15. The method of claim 13 , the method further activating power to the frame buffer in response to a power activation policy being satisfied.
16. The method of claim 15 , wherein the power activation policy is satisfied in response to a refresh time exceeding a refresh interval and the method further activating power to the read circuit in response to the refresh time exceeding the refresh interval.