Method and apparatus for an energy-efficient receiver
View Patent ↗One or more circuits may comprise at least one first-type analog-to-digital converter (ADC) and at least one second-type ADC. The circuit(s) may be operable to receive a plurality of signals, each of which may comprise a plurality of channels. The circuit(s) may be operable to digitize a selected one or more of the channels. Which, if any, of the selected channels are digitized via the at least one first-type ADC and which, if any, of the selected channels are digitized via the at least one second-type ADC, may be based on which of the plurality of channels are the selected channels and/or based on power consumption of the circuit(s). A bandwidth of each first-type ADC may be on the order of the bandwidth of one of the received signals. A bandwidth of each second-type ADC may be on the order of the bandwidth of one of the plurality of channels.
1. A system comprising:
one or more circuits comprising at least one first-type analog-to-digital converter (ADC) and at least one second-type ADC, wherein said one or more circuits are operable to:
receive a plurality of signals, each of said plurality of signals comprising a plurality of channels; and
digitize a selected one or more of said plurality of channels via said at least one first-type ADC and/or said at least one second-type ADC, wherein which, if any, of said selected one or more of said channels are digitized via said at least one first-type ADC and which, if any, of said selected one or more of said channels are digitized via said at least one second-type ADC, is based on which of said plurality of channels are said selected one or more of said channels.
2. The system of claim 1 , wherein:
a bandwidth of each of said at least one first-type ADC is on the order of the bandwidth of one of said plurality of received signals; and
a bandwidth of each of said at least one second-type ADC is on the order of the bandwidth of one of said plurality of channels.
3. The system of claim 2 , wherein:
said bandwidth of one of said plurality of received signals is approximately 1 gigahertz; and
said bandwidth of one of said plurality of channels is approximately in the range of 6 to 45 megahertz.
4. The system of claim 1 , wherein said one or more circuits are operable to determine a threshold based on power consumption of said one or more circuits.
5. The system of claim 1 , wherein:
said one or more circuits comprise at least one first-type mixer and at least one second-type mixer; and
said one or more circuits are operable to downconvert said selected one or more channels via said at least one first-type mixer and/or said at least one second-type mixer, wherein which, if any, of said selected one or more of said channels are downconverted via said at least one first-type mixer and which, if any, of said selected one or more of said channels are downconverted via said at least one second-type mixer, is based on which of said plurality of channels are said selected one or more of said channels.
6. The system of claim 1 , wherein said one or more circuits comprise one or more multiplexers for conveying one or more of said plurality of signals to said at least one first-type ADC and/or to said at least one second-type ADC.
7. The system of claim 1 , wherein each of said plurality of signals is a satellite television signal.
8. The system of claim 1 , wherein said one or more circuits are collocated with a satellite dish.
9. The system of claim 1 , wherein said one or more circuits are integrated on common substrate with a low-noise block downconverter of said satellite dish.
10. A method comprising:
performing via one or more circuits comprising at least one first-type analog-to-digital converter (ADC) and at least one second-type ADC:
receiving a plurality of signals, each of said plurality of signals comprising a plurality of channels; and
digitizing a selected one or more of said plurality of channels via said at least one first-type ADC and/or said at least one second-type ADC, wherein which, if any, of said selected one or more of said channels are digitized via said at least one first-type ADC and which, if any, of said selected one or more of said channels are digitized via said at least one second-type ADC, is based on which of said plurality of channels are said selected one or more of said channels.
11. The method of claim 10 , wherein:
a bandwidth of each of said at least one first-type ADC is on the order of the bandwidth of one of said plurality of received signals; and
a bandwidth of each of said at least one second-type ADC is on the order of the bandwidth of one of said plurality of channels.
12. The method of claim 11 , wherein:
said bandwidth of one of said plurality of received signals is approximately 1 gigahertz; and
said bandwidth of one of said plurality of channels is approximately in the range of 6 to 45 megahertz.
13. The method of claim 10 , comprising determining a threshold based on power consumption of said one or more circuits.
14. The method of claim 10 , wherein said one or more circuits comprise at least one first-type mixer and at least one second-type mixer, the method comprising:
downconverting said selected one or more channels via said at least one first-type mixer and/or said at least one second-type mixer, wherein which, if any, of said selected one or more of said channels are downconverted via said at least one first-type mixer and which, if any, of said selected one or more of said channels are downconverted via said at least one second-type mixer, is based on which of said plurality of channels are said selected one or more of said channels.
15. The method of claim 10 , wherein said one or more circuits comprise one or more multiplexers, the method comprising:
conveying one or more of said plurality of signals to said at least one first-type ADC and/or to said at least one second-type ADC via said one or more multiplexers.
16. The method of claim 10 , wherein each of said plurality of signals is a satellite television signal.
17. The method of claim 10 , wherein said one or more circuits are collocated with a satellite dish.
18. The method of claim 10 , wherein said one or more circuits are integrated on common substrate with a low-noise block downconverter of said satellite dish.