Time management using time-dependent changes to memory
View Patent ↗A time manager controls one or more timing functions on a circuit. The time manager includes a data storage and a time calculator. The data storage device stores a first indication of a performance characteristic of a memory cell at a first time. The data storage device also stores a second indication of the performance characteristic of the memory cell at a second time. The time calculator is coupled to the data storage device. The time calculator calculates a time duration between the first time and the second time based on a change in the performance characteristic of the memory cell from the first indication to the second indication.
1. An integrated circuit for a smart card, the integrated circuit comprising:
a power interface to introduce electrical power to the integrated circuit;
memory cells to store data signals;
a write engine coupled to the memory cells, wherein the write engine is configured to write a first indication that indicates a characteristic of a first memory cell before a power-down period to a second memory cell and to write a second indication that indicates the characteristic of the first memory cell after the power-down period to a third memory cell;
a read engine coupled to the memory cells, wherein the read engine is configured to read the second memory cell and to read the third memory cell; and
time management logic coupled to the memory cells, wherein the time management logic is configured to determine a time lapse based on a change between the first indication read from the second memory cell and the second indication read from the third memory cell.
2. The integrated circuit of claim 1 , wherein the memory cells comprises phase change random access memory (PCRAM).
3. The integrated circuit of claim 1 , wherein the read property comprises a resistance of the at least one memory cell.
4. The integrated circuit of claim 1 , wherein the time management logic is further configured to compare first and second states of a plurality of the memory cells, and determine the time lapse based on a mathematical combination of changes in performance characteristics of the plurality of the memory cells.
5. The integrated circuit of claim 1 , wherein the time management logic is further configured to mathematically derive an overall time duration based on the plurality of preliminary time durations.
6. A method comprising:
storing a first value on an electronic device, wherein the first value is representative of a performance characteristic of a memory element before a power-down period of an electronic device;
obtaining a second value at the electronic device, wherein the second value is representative of the performance characteristic of the memory element after the power-down period of the electronic device; and
deriving a time duration at the electronic device, wherein the time duration is derived based on a difference between the first and second values and corresponds to the power-down period
wherein obtaining the first and second values comprises obtaining first and second resistance values of the memory elements;
wherein deriving the time duration comprises finding a change in the resistance values from the first resistance value to the second resistance value; and
wherein the time duration is derived based on the change in the resistance value.
7. The method of claim 6 , further comprising comparing the derived time duration to a time threshold.
8. The method of claim 7 , further comprising granting access to a component of the electronic device in response to a determination that the derived time duration exceeds the time threshold.
9. The method of claim 7 , further comprising providing an expiration indication in response to a determination that the derived time duration exceeds the time threshold.