IP Library Granted Patent US 9,171,572
Granted Patent B1
US 9,171,572 · App. 14/278,188 · Granted Oct 27, 2015

Multi-dimensional optimization of read channel

Inventors: Wu Chang (Sunnyvale, CA); Parviz Rahgozar (Cupertino, CA); Ming Jin (Fremont, CA); Haitao Xia (San Jose, CA)
Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
G11B20/10509
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Quick Facts
Patent No.
US 9,171,572
App. No.
14/278,188
Granted
Oct 27, 2015
Kind
B1
Abstract

Variations of the Nelder-Mead direct search method are employed to find read channel parameter settings in a discrete field having three or more dimensions. The three or more dimensions correspond to read channel parameters, at least some of which are highly correlated. The steps of the Nelder-Mead method are executed according to a methodology to arrive at substantially optimal parameter settings for a read channel, even where a discrete function defining parameter outcomes is noisy. In some embodiments, dimensional collapse, considered inefficient in a two-dimensional field, is allowed in order to reach an optimal solution in a greater-than-two-dimensional field.

Claims (67)

1. A method for determining read channel parameters in a data storage device, comprising:

receiving a read channel performance function corresponding to at least three read channel performance parameters;

selecting a plurality of vertexes in a discrete, continuous field defined by the read channel performance function;

determining a worst vertex in the plurality of vertexes having a worst performance;

determining if replacing the worst vertex will cause dimensional collapse; and

determining if dimensional collapse is desirable.

2. The method of claim 1 , wherein determining if dimensional collapse is desirable comprises determining if the vertexes satisfy strict dimensional constraints.

3. The method of claim 1 , further comprising:

determining a best vertex in the plurality of vertexes; and

expanding the best vertex according to a central weight of all vertexes in the plurality of vertexes.

4. The method of claim 1 , further comprising:

determining a best vertex in the plurality of vertexes; and

iteratively contracting each vertex in the plurality of vertexes with respect to the best vertex.

5. The method of claim 4 , further comprising:

determining that a pre-determined number of iterations have been executed; and

halting further iterations.

6. The method of claim 4 , further comprising:

logging each vertex used during each iterations; and

rejecting any new vertex previously logged.

7. The method of claim 6 , further comprising selecting a neighboring vertex to the rejected vertex.

8. A data storage device comprising:

a processor;

memory connected to the processor;

a data storage element connected to the processor; and

computer executable program code to configured the processor to:

receive a read channel performance function corresponding to at least three read channel performance parameters;

select a plurality of vertexes in a discrete, continuous field defined by the read channel performance function;

determine a worst vertex in the plurality of vertexes having a worst performance;

determine if replacing the worst vertex will cause dimensional collapse; and

determine if dimensional collapse is desirable.

9. The data storage device of claim 8 , wherein determining if dimensional collapse is desirable comprises determining if the vertexes satisfy strict dimensional constraints.

10. The data storage device of claim 8 , wherein the computer executable program code further configures the processor to:

determine a best vertex in the plurality of vertexes; and

expand the best vertex according to a central weight of all vertexes in the plurality of vertexes.

11. The data storage device of claim 8 , wherein the computer executable program code further configures the processor to:

determine a best vertex in the plurality of vertexes; and

iteratively contract each vertex in the plurality of vertexes with respect to the best vertex.

12. The data storage device of claim 11 , wherein the computer executable program code further configures the processor to:

determine that a pre-determined number of iterations have been executed; and

halt further iterations.

13. The data storage device of claim 11 , wherein the computer executable program code further configures the processor to:

log each vertex used during each iterations; and

reject any new vertex previously logged.

14. The data storage device of claim 13 , wherein the computer executable program code further configures the processor to select a neighboring vertex to the rejected vertex.

15. A computer apparatus comprising:

a processor;

memory connected to the processor;

a data storage element connected to the processor; and

computer executable program code to configured the processor to:

receive a read channel performance function corresponding to at least three read channel performance parameters;

select a plurality of vertexes in a discrete, continuous field defined by the read channel performance function;

determine a worst vertex in the plurality of vertexes having a worst performance;

determine if replacing the worst vertex will cause dimensional collapse; and

determine if dimensional collapse is desirable.

16. The apparatus of claim 15 , wherein determining if dimensional collapse is desirable comprises determining if the vertexes satisfy strict dimensional constraints.

17. The apparatus of claim 15 , wherein the computer executable program code further configures the processor to:

determine a best vertex in the plurality of vertexes; and

expand the best vertex according to a central weight of all vertexes in the plurality of vertexes.

18. The apparatus of claim 15 , wherein the computer executable program code further configures the processor to:

determine a best vertex in the plurality of vertexes; and

iteratively contract each vertex in the plurality of vertexes with respect to the best vertex.

19. The apparatus of claim 18 , wherein the computer executable program code further configures the processor to:

determine that a pre-determined number of iterations have been executed; and

halt further iterations.

20. The apparatus of claim 18 , wherein the computer executable program code further configures the processor to:

log each vertex used during each iterations; and

reject any new vertex previously logged.

Assignments (8)
MERGER Recorded Mar 3, 2023
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; BROADCOM INTERNATIONAL PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 062952/0850 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2020
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
To: BROADCOM INTERNATIONAL PTE. LTD.
Reel/Frame 053771/0901 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047422 FRAME: 0464. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0702 →
MERGER Recorded Oct 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047422/0464 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 15, 2014
From: CHANG, WU; RAHGOZAR, PARVIZ; JIN, MING; XIA, HAITAO
To: LSI CORPORATION
Reel/Frame 032900/0721 →
Continuity (1)
Provisional Application 61989154 · May 6, 2014