OPTIMIZATION OF CIRCUIT LAYOUT AREA OF A MEMORY DEVICE
A memory cell including a storage cell, a write port cell, and a read port cell is discussed. The storage cell is configured to store a logic value. The write port cell is configured to write the logic value. The read port cell is configured to read the stored logic value and includes a plurality of read ports. At least a first port of the plurality of read ports includes a first and a second active diffusion region that are each configured to be used for implementation of a second p-channel transistor. At least a second read port of the plurality of read ports includes a third and fourth active diffusion regions that are each configured to be used for implementation of a second n-channel transistor.
1 . A memory cell, comprising:
a storage cell configured to store a logic value;
a write port cell coupled to the storage cell configured to write the logic value; and
a read port cell coupled to the storage cell configured to read the stored logic value, the read port cell comprising a plurality of read ports,
wherein a first read port of the plurality of read ports includes a first p-channel transistor and a second p-channel transistor, and
wherein a second read port of the plurality of read ports includes a first n-channel transistor and a second n-channel transistor.
2 . The memory cell of claim 1 , wherein a first portion of the plurality of read ports each includes the first p-channel transistor and the second p-channel transistor, and
wherein a second portion of the plurality of read ports each includes the first n-channel transistor and the second n-channel transistor.
3 . The memory cell of claim 1 , wherein the first and the second p-channel transistors and the first and the second n-channel transistors are fin field effect transistors (FinFETs).
4 . The memory cell of claim 1 , wherein the first and the second p-channel transistors and the first and the second n-channel transistors are metal-oxide-semiconductor field effect transistors (MOSFETs).
5 . The memory cell of claim 1 , wherein gates of the first p-channel transistor and the first n-channel transistor are coupled to an output node of the storage cell.
6 . The memory cell of claim 1 , wherein the second p-channel transistor is coupled to a first read bit line (RBL) and a first read word line (RWL), and
wherein the second n-channel transistor is coupled to a second RBL and a second RWL.
7 . The memory cell of claim 6 , wherein the first RBL is configured to be precharged to a first voltage level, and
wherein the second RBL is configured to be precharged to a second voltage level, the second voltage level being different from the first voltage level.
8 . The memory cell of claim 1 , wherein the storage cell comprises:
a feedback loop; and
a switching circuit configured to open the feedback loop during a write mode of operation.
9 . The memory cell of claim 1 , wherein the storage cell comprises:
a feedback loop: and
a reset circuit configured to:
open the feedback loop; and
set a logic value at an input node of the storage cell.
10 . A memory cell, comprising:
a storage cell configured to store a logic value;
a write port cell, coupled to the storage cell, configured to write the logic value; and
a read port cell, coupled to the storage cell, configured to read the stored logic value, the read port cell comprising a plurality of read ports,
wherein a first read port of the plurality of read ports includes a first active diffusion region and a second active diffusion region, the first active diffusion region being configured to be used for implementation of a first p-channel transistor and the second active diffusion region being configured to be used for implementation of a second p-channel transistor, and
wherein a second read port of the plurality of read ports includes a third active diffusion region and a fourth active diffusion region, the third active diffusion region being configured to be used for implementation of a first n-channel transistor and the second active diffusion region being configured to be used for implementation of a second n-channel transistor.
11 . The memory cell of claim 10 , wherein the first and the second active diffusion regions are configured to form a first substantially continuous active diffusion region, and
wherein the third and the fourth active diffusion regions are configured to form a second substantially continuous active diffusion region.
12 . The memory cell of claim 10 , wherein the first and the second p-channel transistors and the first and the second n-channel transistors are metal-oxide-semiconductor field effect transistors (MOSFETs).
13 . The memory cell of claim 10 , wherein the first and the second p-channel transistors and the first and the second n-channel transistors are fin field effect transistors (FinFETs).
14 . The memory cell of claim 10 , wherein a first portion of the plurality of read ports each includes the first p-channel transistor and the second p-channel transistor, and
wherein a second portion of the plurality of read ports each includes the first n-channel transistor and the second n-channel transistor.
15 . The memory cell of claim 10 , wherein the first portion of the plurality of read ports each further includes a first polysilicon region, the first polysilicon region being configured as a first gate region of the first p-channel transistor, and
wherein the second portion of the plurality of read ports each further includes a second polysilicon region, the second polysilicon region being configured as a second gate region of the first n-channel transistor.
16 . The memory cell of claim 15 , wherein the first and the second polysilicon regions are configured to form a substantially continuous polysilicon region.
17 . A semiconductor device, comprising:
a storage cell configured to store a logic value;
a write port cell configured to write the logic value; and
a read port cell configured to read the stored logic value, the read port cell comprising a first read port and a second read port,
wherein the first read port includes a first active diffusion region and a second active diffusion region, the first active diffusion region being configured to be used for implementation of a first p-channel transistor and the second active diffusion region being configured to be used for implementation of a second p-channel transistor, and
wherein the second read port includes a third active diffusion region and a fourth active diffusion region, the third active diffusion region being configured to be used for implementation of a first n-channel transistor and the second active diffusion region being configured to be used for implementation of a second n-channel transistor.
18 . The semiconductor device of claim 17 , wherein the first read port further includes a first polysilicon region, the first polysilicon region being configured as a first gate region of the first p-channel transistor, and
wherein the second read port further includes a second polysilicon region, the second polysilicon region being configured as a second gate region of the first n-channel transistor.
19 . The semiconductor device of claim 18 , wherein the first and the second polysilicon regions are configured to form a substantially continuous polysilicon region.
20 . The semiconductor device of claim 17 , wherein the first and the second p-channel transistors and the first and second n-channel transistors are fin field effect transistors (FinFETs).