IP Library Granted Patent US 9,525,877
Granted Patent B2
US 9,525,877 · App. 14/279,745 · Granted Dec 20, 2016

Video decoder parallelization for tiles

Inventors: Kiran Misra (Vancouver, WA); Christopher A. Segall (Camas, WA)
Assignee: Sharp Kabushiki Kaisha
H04N19/00793H04N19/13H04N19/174H04N19/176H04N19/436H04N19/44H04N19/513H04N19/55H04N19/61H04N19/63H04N19/70H04N19/91
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Quick Facts
Patent No.
US 9,525,877
App. No.
14/279,745
Granted
Dec 20, 2016
Kind
B2
Abstract

A method for decoding video includes receiving a frame of the video that includes at least one slice and at least one tile. Each of the at least one slice and the at least one tile are not all aligned with one another. Each of the at least one slice is characterized that it is decoded independently of the other the at least one slice. Each of the at least one tile is characterized that it is a rectangular region of the frame and having coding units for the decoding arranged in a raster scan order. The at least one tile of the frame are collectively arranged in a raster scan order of the frame.

Claims (9)

1. A method for decoding video using a processor, the method comprising:

(a) receiving a bit-stream of a frame of said video that includes at least one slice and at least one tile, where each of said at least one slice is decoded independently of another one of said at least one slice and includes said at least one tile,

wherein said at least one tile is characterized that it is a rectangular region of said frame and includes coding units for said decoding arranged in a raster scan order;

(b) receiving first information indicating whether location information of said at least one tile is transmitted within said at least one slice;

(c) receiving second information suitable for decoding said at least one tile, said second information including a location of said at least one tile;

(d) receiving a first flag at an end of said at least one tile;

(e) ignoring bits in a bit-stream until reading from a pre-defined position when receiving said first flag, wherein the pre-defined position is a byte aligned position;

(f) initializing a decoding process at a beginning of each of the at least one tile; and

(g) providing a second flag that indicates if tiles are being used.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Jul 26, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: VELOS MEDIA, LLC AND VELOS MEDIA MANAGEMENT, LLC
Reel/Frame 060923/0407 →
SECOND AMENDED AND RESTATED MEMBER INTELLECTUAL PROPERTY SECURITY AGREEMENT Recorded Apr 2, 2018
From: VELOS MEDIA MANAGEMENT, LLC; VELOS MEDIA, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045806/0030 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 30, 2017
From: SHARP CORPORATION
To: VELOS MEDIA, LLC
Reel/Frame 042876/0098 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 30, 2014
From: MISRA, KIRAN; SEGALL, CHRISTOPHER A.
To: SHARP LABORATORIES OF AMERICA, INC.
Reel/Frame 033207/0884 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 30, 2014
From: SHARP LABORATORIES OF AMERICA, INC.
To: SHARP KABUSHIKI KAISHA
Reel/Frame 033207/0893 →
Continuity (2)
Continuation 13180419 · Jul 11, 2011
Related Publication 20140254671A1 · Sep 11, 2014