Boot recovery system
View Patent ↗A boot recovery system includes a serial peripheral interface (SPI) storage that stores a primary boot block. A primary SPI controller is connected to the SPI storage through a primary SPI bus. An embedded controller (EC) includes an EC storage that stores a recovery boot block. The EC is coupled to the primary SPI bus through a secondary SPI bus. The EC is configured to determine that the primary boot block should be replaced, retrieve the recovery boot block from the EC storage, replace the primary boot block in the SPI storage with the recovery boot block through the secondary SPI bus, and initiate an information handling system (IHS) reboot process. The determining, retrieving, replacing, and initiating may be performed by the EC while a processing system that is coupled to the primary SPI controller is not in an operating mode.
1. A boot recovery system, comprising:
a serial peripheral interface (SPI) storage that stores a primary boot block;
a primary SPI controller connected to the SPI storage through a primary SPI bus;
an embedded controller (EC) that includes an EC storage that stores a recovery boot block, and an EC processing system that is coupled to the SPI storage through:
a secondary SPI bus that directly connects the EC processing system to a secondary SPI controller;
a primary/secondary SPI controller coupling that directly connects the secondary SPI controller to the primary SPI controller; and
the primary SPI bus that directly connects the primary SPI controller to the SPI storage; and
a host processing system that is directly connected to the secondary SPI controller through a secondary SPI controller/host processing system bus that, along with the secondary SPI bus, allows the host processing system to access the EC directly when the host processing system is in an operational mode, wherein the EC processing system is configured to hold the host processing system in a non-operational mode and:
determine that the primary boot block should be replaced;
retrieve the recovery boot block from the EC storage;
replace the primary boot block in the SPI storage with the recovery boot block through the secondary SPI bus, the primary/secondary SPI controller coupling, and the primary SPI bus; and
initiate an information handling system (IHS) reboot process.
2. The boot recovery system of claim 1 , wherein the EC processing system is further configured to:
monitor an IHS boot process that uses the primary boot block through the secondary SPI bus.
3. The boot recovery system of claim 1 , wherein the EC processing system is configured to determine that the primary boot block should be replaced in response to at least one of:
receiving a command to replace the primary boot block;
determining that the primary boot block is not valid; and
determining that a timer was tripped during a previous IHS boot process.
4. The boot recovery system of claim 1 , wherein the secondary SPI bus provides a direct access interface for the EC processing system to determine that the primary boot block should be replaced and access the SPI storage to replace the primary boot block with the recovery boot block.
5. The boot recovery system of claim 1 , wherein the EC processing system is further configured to:
determine that the primary boot block does not need to be replaced;
cause the host processing system that is coupled to the primary SPI controller to enter an operating mode; and
determine whether a timer has expired.
6. The boot recovery system of claim 5 , wherein the EC processing system is further configured to:
determine that the timer has not expired and, in response, cancel the timer and allow an IHS boot process that uses the primary boot block to proceed; and
determine that the timer has expired and, in response, set a timer-trip flag and cause the IHS boot process that uses the primary boot block to reboot.
7. An information handling system (IHS), comprising:
a processing system;
a primary boot block storage that stores a primary boot block;
a primary serial peripheral interlace (SPI) controller directly connected to the primary boot block storage through a primary SPI bus;
a secondary SPI controller directly connected to the primary SPI controller through a primary/secondary SPI controller coupling;
an embedded controller (EC) that includes an EC storage that stores a recovery boot block, wherein the EC is coupled to the primary boot block storage through a secondary SPI bus that is directly connected to the secondary SPI controller, the primary/secondary SPI controller coupling, and the primary SPI bus;
a processing system that is directly connected to the secondary SPI controller through a secondary SPI controller/processing system bus,
wherein the secondary SPI controller provides the processing system with direct access to the EC when the processing system is in at least one operating mode, and
wherein the EC is configured, while a processing system is not in the at least one operating mode, to:
determine that the primary boot block should be replaced;
retrieve the recovery boot block from the EC storage;
replace the primary boot block in the primary boot block storage with the recovery boot block through the secondary SPI bus, the primary/secondary SPI controller coupling, and the primary SPI bus; and
initiate an information handling system (IHS) reboot process.
8. The IHS of claim 7 , wherein the EC is further configured to:
monitor an IHS boot process that uses the primary boot block through the secondary SPI bus.
9. The IHS of claim 7 , wherein the EC is configured to determine that the primary boot block should be replaced in response to at least one of:
receiving a command to replace the primary boot block;
determining that the primary boot block is not valid; and
determining that a timer was tripped during a previous IHS boot process.
10. The IHS of claim 7 , wherein the EC if further configured to:
hold the processing system in a reset mode such that the processing system is not in the operating mode.
11. The IHS of claim 7 , wherein the EC is further configured to:
determine that the primary boot block does not need to be replaced;
cause the processing system to enter an operating mode; and
determine whether a timer has expired.
12. The IHS of claim 11 , wherein the EC is further configured to:
determine that the timer has not expired and, in response, cancel the timer and allow an IHS boot process that uses the primary boot block to proceed; and
determine that the timer has expired and, in response, set a timer-trip flag and cause the IHS boot process that uses the primary boot block to reboot.
13. A method for boot recovery, comprising:
causing, by an embedded controller (EC), a host processing system to remain in a non-operational mode;
determining, by the EC while the host processing system is in the non-operational mode, that a primary boot block should be replaced;
retrieving, by the EC while the host processing system is in the non-operational mode, a recovery boot block from an EC storage included in the EC;
replacing, by the EC while the host processing system is in the non-operational mode, the primary boot block with the recovery boot block in a primary boot block storage via:
a secondary serial peripheral interface (SPI) bus that is directly connected to a secondary SPI controller;
a primary/secondary SPI controller coupling that directly connects the secondary SPI controller to a primary SPI controller; and
a primary SPI bus that directly connects the primary SPI controller to the primary boot block storage;
initiating, by the EC while the host processing system is in the non-operational mode, an information handling system (IHS) reboot process; and
providing, by the EC while the host processing system is in an operational mode, the host processing system with direct access to the EC through a secondary SPI controller/host processing system bus that directly connects the host processing system to the secondary SPI controller.
14. The method of claim 13 , further comprising:
monitoring, by the EC through the secondary SPI bus, an IHS boot process that uses the primary boot block.
15. The method of claim 13 , wherein the determining, by the EC, that the primary boot block should be replaced includes at least one of:
receiving, by the EC, a command to replace the primary boot block;
determining, by the EC, that the primary boot block is not valid; and
determining, by the EC, that a timer was tripped during a previous IHS boot process.
16. The method of claim 13 , wherein the secondary SPI bus provides a direct access interface for the EC to determine that the primary boot block should be replaced and access the primary boot block storage to replace the primary boot block with the recovery boot block.
17. The method of claim 13 , further comprising:
determining, by the EC, that the primary boot block does not need to be replaced;
causing, by the EC, a processing system that is coupled to the secondary SPI bus to enter an operating mode; and
determining, by the EC, whether a timer has expired.
18. The method of claim 17 , further comprising:
determining, by the EC, that the timer has not expired and, in response, cancelling the timer and allowing an IHS boot process that uses the primary boot block to proceed; and
determining, by the EC, that the timer has expired and, in response, setting a timer-trip flag and causing the IHS boot process that uses the primary boot block to reboot.