IP Library › Granted Patent US 8,987,877
Granted Patent B2
US 8,987,877 · App. 14/280,244 · Granted Mar 24, 2015

Semiconductor device

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Quick Facts
Patent No.
US 8,987,877
App. No.
14/280,244
Granted
Mar 24, 2015
Kind
B2
Abstract

A semiconductor device of the present invention comprises: an outer package; a first lead frame including a first relay lead, a first die pad with a power element mounted thereon, and a first external connection lead which has an end protruding from the outer package; and a second lead frame including a second relay lead, a second die pad with a control element mounted thereon, and a second external connection lead which has an end protruding from the outer package, wherein the first die pad and the second die pad or the first external connection lead and the second relay lead are joined to each other at a joint portion, and an end of the second relay lead extending from a joint portion with the first relay lead is located inside the outer package.

Claims (15)

1. A semiconductor device comprising:

a resin outer package;

a first lead frame including first relay leads, a first die pad with a first semiconductor chip mounted thereon, and first external connection leads which each have an end protruding from the outer package; and

a second lead frame including a second relay lead, a second die pad with a second semiconductor mounted thereon and a suspended lead, and second external connection leads which each have an end protruding from the outer package, wherein

the outer package seals the first semiconductor chip and the second semiconductor chip,

the first die pad and the second die pad are jointed at a first joint portion, the first relay lead and the second relay lead are jointed at a second joint portion and are electrically connected, and

ends of the second relay lead and ends of the suspended lead are located inside the outer package.

2. The semiconductor device according to claim 1 , wherein the first relay lead, the first semiconductor chip, and the first external connection lead are electrically connected, and the second relay lead, the second semiconductor chip, and the second external connection lead are electrically connected.

3. The semiconductor device according to claim 1 , wherein the first lead frame and the second lead frame are stacked.

4. The semiconductor device according to claim 1 , wherein at least a portion of the first semiconductor chip and at least a portion of the second semiconductor chip are disposed so as to overlap each other in a plan view.

5. The semiconductor device according to claim 1 , wherein the first relay lead of the first lead frame and the second relay lead of the second lead frame are jointed to each other with caulking.

6. The semiconductor device according to claim 1 , wherein the first relay lead of the first lead frame and the second relay lead of the second lead frame are jointed to each other with surface joining.

7. The semiconductor device according to claim 1 , wherein the first relay leads and the first die pad of the first lead frame are coupled to a heat dissipation plate which is partly exposed from a surface of the outer package.

8. The semiconductor device according to claim 1 , wherein one of the ends of the second relay lead and one of the ends of the suspended lead are located higher than the first die pad in a thickness direction of the device.

9. The semiconductor device according to claim 1 , wherein the second relay lead and the suspended lead are completely embedded in the outer package.