Method to dynamically update LLRs in an SSD drive and/or controller
View Patent ↗An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/write operations. The memory comprises a plurality of memory units each having a size less than a total size of the memory. The controller may be configured to perform a first error correction code decoding on the memory units using a plurality of initial log likelihood ratio values. The controller may be configured to count a number of unsatisfied checks if the first error correction code decoding fails. The controller may be configured to generate a plurality of measured log likelihood ratio values if the number of unsatisfied checks is below a threshold. The plurality of measured log likelihood ratio values are (a) based on calculations using decoded bits of the first error correction code decoding, and (b) used to perform a second error correction code decoding on the memory units.
1. An apparatus comprising:
a memory configured to store data the memory comprising a plurality of memory units each having a size less than a total size of the memory; and
a controller configured to (i) process a plurality of read/write operations, (ii) perform a first error correction code decoding on the memory units using a plurality of initial log likelihood ratio values, (iii) count a number of unsatisfied checks if the first error correction code decoding fails, (iv) generate a plurality of measured log likelihood ratio values if the number of unsatisfied checks is below a threshold, wherein the plurality of measured log likelihood ratio values are (a) based on calculations using decoded bits of the first error correction code decoding, and (b) used to perform a second error correction code decoding on the memory units.
2. The apparatus according to claim 1 , wherein the decoded bits of the first error correcting code decoding are used as genie data.
3. The apparatus according to claim 2 , wherein the decoded bits of the first error correcting code decoding used as the genie data have errors.
4. The apparatus according to claim 1 , wherein the controller is further configured to track histograms for the memory units.
5. The apparatus according to claim 4 , wherein the plurality of measured log likelihood ratio values are generated using the histograms.
6. The apparatus according to claim 4 , wherein the histograms are aggregated based on a plurality of the memory units.
7. The apparatus according to claim 1 , wherein the measured log likelihood ratio values are dynamically generated.
8. The apparatus according to claim 1 , wherein the number of unsatisfied checks positively correlates to a number of erroneous bits.
9. The apparatus according to claim 8 , wherein the erroneous bits are caused by trapping sets.
10. The apparatus according to claim 1 , wherein the decoded bits of the first error correction code decoding are treated as correct.
11. The apparatus according to claim 1 , wherein the measured log likelihood ratio values handle a time-varying property of the memory.
12. The apparatus according to claim 1 , wherein the apparatus reduces an uncorrectable bit error rate.
13. The apparatus according to claim 1 , wherein the controller uses the measured log likelihood ratio values for error recovery.
14. The apparatus according to claim 1 , wherein the controller is further configured to implement alternate error recovery if the number of unsatisfied checks is above the threshold.
15. The apparatus according to claim 1 , wherein the measured log likelihood ratio values are close to optimal even if a voltage distribution of a plurality of cells of the memory units has changed.
16. The apparatus according to claim 1 , wherein the apparatus is configured to dynamically update log likelihood ratio values.
17. A method to dynamically update log likelihood ratio values, comprising the steps of:
configuring a memory to process a plurality of read/write operations, the memory comprising a plurality of memory units each having a size less than a total size of the memory;
performing a first error correction code decoding on the memory using a plurality of initial log likelihood ratio values;
counting a number of unsatisfied checks if the first error correction code decoding fails; and
generating a plurality of measured log likelihood ratio values if the number of unsatisfied checks is below a threshold, wherein the measured plurality of log likelihood ratio values are (a) based on calculations using decoded bits of the first error correction code decoding, and (b) used to perform a second error correction code decoding on the memory.
18. An apparatus comprising:
an interface configured to process a plurality of read/write operations to/from a memory; and
a control circuit configured to (i) perform a first error correction code decoding on the memory using a plurality of initial log likelihood ratio values, (ii) count a number of unsatisfied checks if the first error correction code decoding fails, (iii) generate a plurality of measured log likelihood ratio values if the number of unsatisfied checks is below a threshold, wherein the measured plurality of log likelihood ratio values are (a) based on calculations using decoded bits of the first error correction code decoding, and (b) used to perform a second error correction code decoding on the memory.