Decoding and optimized implementation of SECDED codes over GF(q)
View Patent ↗A plurality of columns for a check matrix that implements a distance d linear error correcting code are populated by providing a set of vectors from which to populate the columns, and applying to the set of vectors a filter operation that reduces the set by eliminating therefrom all vectors that would, if used to populate the columns, prevent the check matrix from satisfying a column-wise linear independence requirement associated with check matrices of distance d linear codes. One of the vectors from the reduced set may then be selected to populate one of the columns. The filtering and selecting repeats iteratively until either all of the columns are populated or the number of currently unpopulated columns exceeds the number of vectors in the reduced set. Columns for the check matrix may be processed to reduce the amount of logic needed to implement the check matrix in circuit logic.
1. A method for determining whether a syndrome produced from check symbols associated with a linear code divides a column of a check matrix used to produce the check symbols, comprising:
providing pre-computed multiplicative inverses of symbols in said column of the check matrix;
multiplying said multiplicative inverses by respectively corresponding symbols of said syndrome in parallel to produce parallel multiplication results; and
determining whether said parallel multiplication results are equal to one another.
2. An apparatus for determining whether a syndrome produced from check symbols associated with a linear code divides a column of a check matrix used to produce the check symbols, comprising:
a first input for providing pre-computed multiplicative inverses of symbols in said column of the check matrix;
a second input for providing symbols of said syndrome;
parallel multiplication logic coupled to said first and second inputs and configured to multiply said multiplicative inverses by respectively corresponding said syndrome symbols in parallel to produce parallel multiplication results; and
a comparator coupled to said parallel multiplication logic and configured to determine whether said parallel multiplication results are equal to one another.