Digital PLL with hybrid phase/frequency detector and digital noise cancellation

1. A phase locked-loop (PLL) comprising:

a digitally controlled oscillator (DCO) configured to generate a DCO output frequency in response to a tuning input;

a frequency reference oscillator configured to generate a reference frequency input;

a mixed analog/digital signal Delta-Sigma (ΔΣ) Phase/Frequency Detector (ΔΣ PFD) configured to generate a digital output of frequency difference between the reference frequency input and the DCO frequency output, the ΔΣ PFD comprising:

a digital requantizer configured to change a quantization resolution of a feedback portion of the digital output; and

a feedback path configured to receive the feedback portion after the quantization resolution is changed;

an accumulator configured to generate digital phase and frequency error information by accumulating the ΔΣ PFD digital output combined with a digital indicator of a targeted output frequency for the DCO; and

a loop filter following the accumulator and configured to tune phase/frequency of the DCO in response to digital phase and frequency error information.

2. The PLL of claim 1 , where the ΔΣ comprises an analog to digital converter (ADC) for digitizing analog phase error and frequency error information.

3. The PLL of claim 2 , where the ADC is configured to selectively operate in:

a fine resolution mode providing a fine mode number of quantization levels; and

a coarse resolution mode providing fewer quantization levels than the fine mode number of quantization levels.

4. The PLL of claim 3 , where the coarse resolution mode provides at least two quantization levels and the fine resolution mode provides at least four quantization levels.

5. The PLL of claim 2 , where the ADC comprises a Delta-Sigma (ΔΣ) ADC.

6. The PLL of claim 5 , where the ΔΣ PFD further comprises a charge-pump configured to drive the ΔΣ ADC.

7. The PLL of claim 6 , where the ΔΣ PFD further comprises a multi-modulus divider (MMD) configured to receive and divide the DCO output frequency.

8. The PLL of claim 7 , where ΔΣ PFD further comprises a fine resolution encoder circuit configured to interface the ΔΣ ADC output to a control input of the MMD.

9. The PLL of claim 8 , where the ΔΣ PFD comprises a phase and frequency detector (PFD) charge-pump front-end driven by the reference frequency input and a feedback output of the MMD.

10. The PLL of claim 9 , where the PFD charge-pump front-end drives a ΔΣ ADC in communication with the fine resolution encoder.

11. The PLL of claim 1 , where the detector comprises an adaptive filter configured to cancel noise affecting the detector.

12. A method comprising:

performing phase/frequency detection with respect to a reference frequency and a feedback signal;

performing digital requantization between a fine resolution analog-to-digital conversion for the phase/frequency detection and a course resolution digital-to-analog conversion for interfacing with the feedback signal;

generating a multiple bit error encoding of phase/frequency error responsive to the detection;

receiving the multiple bit error encoding at a loop filter; and

controlling a digitally controlled oscillator (DCO) with the loop filter to generate a reference frequency output.

13. The method of claim 12 , further comprising:

generating the feedback signal by applying a multi-modulus divider (MMD) to the reference frequency output.

14. The method of claim 13 , further comprising:

dithering the multiple bit error encoding to interface the MMD.

15. The method of claim 12 , further comprising:

prior to performing digital requantization, configuring an analog-to-digital converter (ADC) to generate the fine resolution analog-to-digital conversion characterized by a greater quantization resolution than the coarse resolution digital-to-analog conversion.

16. The method of claim 12 , further comprising:

performing adaptive noise filtering and cancellation of noise affecting the phase/frequency detection.

17. A phase locked loop (PLL) comprising:

a reference frequency input;

a phase and frequency detector charge-pump in communication with the reference frequency input;

a delta sigma analog-to-digital converter (ADC) driven by the charge-pump, the ADC comprising a resolution mode input configured to selectively change the ADC between:

a fine resolution mode providing a fine mode number of quantization levels for phase and frequency error; and

a coarse resolution mode providing fewer quantization levels for the phase and frequency error than the fine mode number of quantization levels;

a loop filter following the ADC and configured to accept the phase and frequency error and responsively drive a digitally controlled oscillator (DCO) that generates a reference frequency output; and

a feedback path from the DCO to the charge-pump, the feedback path comprising a multi-modulus divider (MMD).

18. The PLL of claim 17 , further comprising a dither circuit configured to interface the fine mode number of quantization levels to a lower-resolution MMD control grid of the MMD.

19. The PLL of claim 1 , where the accumulator further comprises an input configured to receive a phase lock signal to selectively disable the accumulator.

20. The method of claim 16 , where:

performing adaptive noise filtering and cancellation comprises applying an adaptive algorithm to determine filter coefficients; and

the adaptive algorithm comprises a Least Mean Squares algorithm, a Recursive Least Squares algorithm, or both.

21. A phase locked loop (PLL) comprising:

a reference frequency input;

a detector in communication with the reference frequency input, the detector comprising:

a fine resolution encoder configured to output a multiple bit resolution phase/frequency error encoding; and

a phase and frequency detector including an analog to digital converter (ADC), the ADC is configured to selectively operate in:

a fine resolution mode providing a fine mode number of quantization levels; and

a coarse resolution mode providing fewer quantization levels than the fine mode number of quantization levels;

a loop filter following the detector and configured to accept the multiple bit resolution error encoding; and

a reference frequency output following the loop filter.