Methods, Circuits, Devices and Systems for Comparing Signals
Disclosed is a method of comparing two or more signals which may include: for each of the two or more signals, charging to a fixed voltage a compensation capacitor associated with a sense path of the signal, discharging each of the charged capacitors to a threshold voltage of a transistor in its respective sense path and integrating a discharge current from each capacitor with the signal sensed on the respective sense path.
1 . A method of comparing two or more signals, said method comprising:
for each of the two or more signals, charging to a fixed voltage a compensation capacitor associated with a sense path of the signal;
discharging each of the charged capacitors to a threshold voltage of a transistor in its respective sense path; and
integrating a discharge current from each capacitor with the signal sensed on the respective sense path
2 . The method according to claim 1 , further comprising enabling a cross coupled latch to increase the gain between the two signals.
3 . The method according to claim 2 , further comprising latching the input to create a substantially digital output.
4 . The method according to claim 2 , wherein the signal sensed on the respective sense path develops substantially continuously.
5 . The method according to claim 4 , wherein the signal sensed develops substantially linearly.
6 . The method according to claim 3 , further comprising switching a group of switches to a first charging state to enable said charging and switching the group of switches to a second discharging state to enable said discharging.
7 . The method according to claim 6 , further comprising switching the group of switches to increase said gain and switching the group of switches to enable said latching.
8 . A method of comparing two signals using a quadrangular sensing scheme, said method comprising:
charging first and second offset compensated capacitors;
transistor-dependent discharging of the first and second capacitors to threshold voltage of associated respective first and second transistors and simultaneously enabling respective first and second input signals development on respective first and second bit lines;
enabling cross coupling of the first and second transistors to enable continuous first and second signal development and increased gain between the first and second input signals; and
latching of the first and second inputs so that a substantially digital output is detected.
9 . The method according to claim 6 , wherein the first and second input signals develop substantially linearly.
10 . A comparator comprising:
a first branch including a first transistor coupled to a first capacitor to be selectively charged to a threshold voltage of said first transistor, said first branch connectable to a first bit line;
a second branch cross coupled to said first branch via a first and second cross-coupling connection lines, said second branch including a second transistor coupled to a second capacitor to be selectively charged to a threshold voltage of said second transistor, said second branch connectable to a second bit line; and
a first set of switches including one or more sets of switches that when in an amplifying state cause said first and second transistors to amplify a first input on said first bit line and a second input on said second bit line, wherein each pair of switches includes a first and second switch associated with said first and second branch respectively.
11 . The comparator according to claim 10 , further comprising at least one pull-down switch that when in a latching state causes said first branch and said second branch to latch.
12 . The comparator of claim 11 , wherein said first branch further includes a first pull-down Nmos transistor and said second branch includes a second pull-down Nmos transistor.
13 . The comparator of claim 10 , wherein said first input and said second input develop substantially linearly.
14 . The comparator of claim 10 , wherein said one or more pairs of switches are operable in a charging state to charge said first and second capacitors.
15 . The comparator of claim 14 , wherein said one or more pairs of switches are operable in a discharging state to discharge said first and second capacitors to a threshold voltage of said second transistor.
16 . The comparator of claim 10 , wherein said first input and said first cross coupling connection line are connected directly.
17 . The comparator of claim 10 , wherein said first capacitor is connected directly to a gate of said first transistor and selectively connectable indirectly to supply voltages.
18 . The comparator according to claim 10 , further comprising at least one pull-up switch that when in a latching state causes said first branch and said second branch to latch.
19 . The comparator of claim 11 , wherein said first branch further includes a first pull-up Pmos transistor and said second branch includes a second pull-up Pmos transistor.