Array substrate, display panel and display device
View Patent ↗An array substrate is disclosed. The array substrate includes a non-display region surrounding a display region. The array substrate also includes gate lines in the display region, and a gate drive circuit and a bus electrically insulated from the gate lines and a gate drive circuit in the non-display region. The gate lines extend into the non-display region and are electrically connected to the gate drive circuit, and each of the gate lines crosses the bus in a first overlap region. The array substrate also includes auxiliary electrode line segments between the bus and the display region. The auxiliary electrode line segments are electrically insulated from one another and from the gate lines, and the auxiliary electrode line segments are disposed in either of a same conductive layer as the bus, or a layer between the conductive layer of the bus and a conductive layer of the gate lines are disposed.
1. An array substrate, comprising:
a display region;
a non-display region, wherein the non-display region surrounds the display region;
a first overlap region;
a plurality of second overlap regions;
a plurality of gate lines in the display region;
a bus electrically insulated from the gate lines in the non-display region;
a gate drive circuit in the non-display region;
wherein the gate lines extend into the non-display region and are electrically connected to the gate drive circuit, wherein each of the gate lines crosses the bus in the first overlap region;
a plurality of auxiliary electrode line segments between the bus and the display region, wherein the auxiliary electrode line segments are electrically insulated from one another and from the gate lines, and wherein the auxiliary electrode line segments are disposed in either of:
a) a same conductive layer as the bus, or
b) a layer between the conductive layer of the bus and a conductive layer of the gate lines are disposed,
wherein each of the gate lines crosses a different one of the auxiliary electrode line segments in a different one of the plurality of second overlap regions.
2. The array substrate according to claim 1 , wherein the bus and the auxiliary electrode line segments are disposed in a same conductive layer.
3. The array substrate according to claim 2 , wherein in a region where the auxiliary electrode line segments are disposed, the array substrate sequentially comprises along a direction of light transmission:
a transparent substrate;
the auxiliary electrode line segments on a surface of the transparent substrate;
an insulating layer covering the auxiliary electrode line segments;
the gate lines on the insulating layer; and
a passivation layer covering a surface of the gate lines.
4. The array substrate according to claim 3 , further comprising an amorphous silicon layer between the insulating layer and the gate lines, wherein the amorphous silicon layer is disposed on a surface of the insulating layer, and the gate lines are disposed on a surface of the amorphous silicon layer.
5. The array substrate according to claim 2 , wherein in a region where the auxiliary electrode line segments are disposed, the array substrate sequentially comprises along a direction of light transmission:
a transparent substrate;
the gate lines disposed on a surface of the transparent substrate;
an insulating layer covering a surface of the gate lines;
the auxiliary electrode line segments on the insulating layer; and
a passivation layer covering a surface of the auxiliary electrode line segments.
6. The array substrate according to claim 5 , further comprising an amorphous silicon layer between the insulating layer and the auxiliary electrode line segments, wherein the amorphous silicon layer is disposed on a surface of the insulating layer, and the auxiliary electrode line segments are disposed on a surface of the amorphous silicon layer.
7. A display panel comprising an array substrate, the array substrate comprising:
a display region;
a non-display region, wherein the non-display region surrounds the display region;
a first overlap region;
a plurality of second overlap regions;
a plurality of gate lines in the display region;
a bus electrically insulated from the gate lines in the non-display region;
a gate drive circuit in the non-display region;
wherein the gate lines extend into the non-display region and are electrically connected to the gate drive circuit, wherein each of the gate lines crosses the bus in the first overlap region;
a plurality of auxiliary electrode line segments between the bus and the display region, wherein the auxiliary electrode line segments are electrically insulated from one another and from the gate lines, and wherein the auxiliary electrode line segments are disposed in either of:
a) a same conductive layer as the bus, or
b) a layer between the conductive layer of the bus and a conductive layer of the gate lines are disposed,
wherein each of the gate lines crosses a different one of the auxiliary electrode line segments in a different one of the plurality of second overlap regions.
8. The array substrate according to claim 7 , wherein the bus and the auxiliary electrode line segments are disposed in a same conductive layer.
9. The array substrate according to claim 8 , wherein in a region where the auxiliary electrode line segments are disposed, the array substrate sequentially comprises along a direction of light transmission:
a transparent substrate;
the auxiliary electrode line segments on a surface of the transparent substrate;
an insulating layer covering the auxiliary electrode line segments;
the gate lines on the insulating layer; and
a passivation layer covering a surface of the gate lines.
10. The array substrate according to claim 9 , further comprising an amorphous silicon layer between the insulating layer and the gate lines, wherein the amorphous silicon layer is disposed on a surface of the insulating layer, and the gate lines are disposed on a surface of the amorphous silicon layer.
11. The array substrate according to claim 8 , wherein in a region where the auxiliary electrode line segments are disposed, the array substrate sequentially comprises along a direction of light transmission:
a transparent substrate;
the gate lines disposed on a surface of the transparent substrate;
an insulating layer covering a surface of the gate lines;
the auxiliary electrode line segments on the insulating layer; and
a passivation layer covering a surface of the auxiliary electrode line segments.
12. The array substrate according to claim 11 , further comprising an amorphous silicon layer between the insulating layer and the auxiliary electrode line segments, wherein the amorphous silicon layer is disposed on a surface of the insulating layer, and the auxiliary electrode line segments are disposed on a surface of the amorphous silicon layer.
13. A display device comprising a display panel, the display panel comprising an array substrate, and the array substrate comprising:
a display region;
a non-display region, wherein the non-display region surrounds the display region;
a first overlap region;
a plurality of second overlap regions;
a plurality of gate lines in the display region;
a bus electrically insulated from the gate lines in the non-display region;
a gate drive circuit in the non-display region;
wherein the gate lines extend into the non-display region and are electrically connected to the gate drive circuit, wherein each of the gate lines crosses the bus in the first overlap region;
a plurality of auxiliary electrode line segments between the bus and the display region, wherein the auxiliary electrode line segments are electrically insulated from one another and from the gate lines, and wherein the auxiliary electrode line segments are disposed in either of:
a) a same conductive layer as the bus, or
b) a layer between the conductive layer of the bus and a conductive layer of the gate lines are disposed,
wherein each of the gate lines crosses a different one of the auxiliary electrode line segments in a different one of the plurality of second overlap regions.
14. The array substrate according to claim 13 , wherein the bus and the auxiliary electrode line segments are disposed in a same conductive layer.